R8CSLASH20 datasheet(228/501 Pages) RENESAS

228 / 501 page

R8C/20 Group, R8C/21 Group

14. Timers

Rev.2.00 Aug 27, 2008

Page 212 of 458

REJ09B0250-0200

Figure 14.75

Operating Example of PWM Mode (Duty 0%, Duty 100%)

Value in TRDi register

m: Setting value in TRDGRAi register

Set to 0 by a program

Rewrite by a program

0000h

Duty 0 %

TRDGRBi register

IMFA bit in

TRDSRi register

IMFB bit in

TRDSRi register

TSTARTi bit in

TRDSTR register

TRDIOBi output

p (p > m)

Since the compare match in the TRDGRBi register is

not generated, “L” is not applied to TRDIOBi output

Value in TRDi register

0000h

TRDGRBi register

IMFA bit in

TRDSRi register

IMFB bit in

TRDSRi register

TSTARTi bit in

TRDSTR register

TRDIOBi output

“L” is applied to TRDIOBi output by the compare

match in the TRDGRBi register with no change.

i = 0 or 1

The above applies to the following conditions:

The EBi bit in the TRDOER1 register is set to 0. (Enable TRDIOBi output.)

The POLB bit in the TRDPOCRi register is set to 0. (active level “L”)

Rewrite by a program

Set to 0 by a program

When the compare matches in the TRDGRAi and TRDGRBi registers are generated

simultaneously, the compare match in the TRDGRBi register has a priority.

“L” is applied to TRDIOBi output without any change.

Duty 100 %

Set to 0 by a program

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