ISL854102DEMO2Z datasheet(16/21 Pages) RENESAS

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ISL854102

FN8870 Rev.1.00

Page 16 of 21

Mar 15, 2019

Table 3 shows the recommended switching frequencies for the

various VOUT to operate up to the maximum VIN (40V).

Synchronization Control

The frequency of operation can be synchronized up to 2MHz by

an external signal applied to the SYNC pin. The rising edge on the

SYNC triggers the rising edge of PHASE. To properly synchronize,

the external source must be at least 10% greater than the

programmed free running IC frequency.

Output Inductor Selection

The inductor value determines the converter’s ripple current.

Choosing an inductor current requires a somewhat arbitrary

choice of ripple current,

I. A reasonable starting point is 30% of

total load current. The inductor value can then be calculated

using Equation 7:

Increasing the value of inductance reduces the ripple current and

thus, the ripple voltage. However, the larger inductance value

may reduce the converter’s response time to a load transient.

The inductor current rating should be such that it does not

saturate in overcurrent conditions. For typical ISL854102

applications, inductor values generally lie in the 10µH to 47µH

range. In general, higher VOUT causes higher inductance.

Buck Regulator Output Capacitor Selection

An output capacitor is required to filter the inductor current. The

current mode control loop allows the use of low ESR ceramic

capacitors and thus supports very small circuit implementations

on the PC board. Electrolytic and polymer capacitors can also be

used.

While ceramic capacitors offer excellent overall performance

and reliability, the actual in-circuit capacitance must be

considered. Ceramic capacitors are rated using large

peak-to-peak voltage swings and with no DC bias. In the DC/DC

converter application, these conditions do not reflect reality. As a

result, the actual capacitance may be considerably lower than

the advertised value. Consult the manufacturer’s datasheet to

determine the actual in-application capacitance. Most

manufacturers publish capacitance vs DC bias so that this effect

can be easily accommodated. The effects of AC voltage are not

frequently published, however, an assumption of ~20% further

reduction generally suffices. The result of these considerations

may mean an effective capacitance 50% lower than nominal and

this value should be used in all design calculations. Nonetheless,

ceramic capacitors are a very good choice in many applications

due to their reliability and extremely low ESR.

Use the following equations to calculate the required

capacitance for ripple voltage. Additional capacitance can be

used.

For the ceramic capacitors (low ESR):

where

I is the inductor’s peak-to-peak ripple current, fSW is the

switching frequency and COUT is the output capacitor.

If using electrolytic capacitors,

Loop Compensation Design

When COMP is not connected to VCC, the COMP pin is active for

external loop compensation. The ISL854102 uses constant

frequency peak current mode control architecture to achieve a

fast loop transient response. An accurate current sensing pilot

device in parallel with the upper MOSFET is used for peak current

control signal and overcurrent protection. The inductor is not

considered as a state variable since its peak current is constant,

and the system becomes a single order system. It is much easier

to design a Type II compensator to stabilize the loop than to

implement voltage mode control. Peak current mode control has

an inherent input voltage feed-forward function to achieve good

line regulation. Figure 36 shows the small signal model of the

synchronous buck regulator.

TABLE 3. RECOMMENDED SWITCHING FREQUENCIES FOR VARIOUS

VOUT

VIN (max) (V)

VOUT (V)

fSW (kHz)

500

3.3

500

2.5

500

1.8

300

VIN min



VOUT

1fSW

–

tMIN_OFF



---------------------------------------------------

(EQ. 6)

(EQ. 7)

VIN VOUT

–

fSW I



--------------------------------

VOUT

VIN

----------------



VOUTripple

I

8fSWCOUT

-------------------------------------

(EQ. 8)

VOUTripple I*ESR

(EQ. 9)

Vin

1:D

-Av(S)

Vcomp

He(S)

Ti(S)

Tv(S)

1:D

-Av(S)

He(S)

T(S)

V^^

FIGURE 36. SMALL SIGNAL MODEL OF SYNCHRONOUS BUCK

REGULATOR

RLP

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