ISL854102DEMO2Z datasheet(15/21 Pages) RENESAS

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ISL854102

FN8870 Rev.1.00

Page 15 of 21

Mar 15, 2019

Overcurrent Protection

During PWM on-time, current through the upper FET is monitored

and compared to a nominal 1.6A peak overcurrent limit. In the

event that current reaches the limit, the upper FET is turned off

until the next switching cycle. In this way, FET peak current is

always well limited.

If the overcurrent condition persists for 17 sequential clock

cycles, the regulator begins its hiccup sequence. In this case,

both FETs are turned off and PG is pulled low. This condition is

maintained for eight soft-start periods, after which the regulator

attempts a normal soft-start.

if output fault persists, the regulator repeats the hiccup

sequence indefinitely. There is no danger even if the output is

shorted during soft-start.

If VOUT is shorted very quickly, FB may collapse below 5/8ths of

its target value before 17 cycles of overcurrent are detected. The

ISL854102 recognizes this condition and begins to lower its

switching frequency proportional to the FB pin voltage. This

adjustment ensures that the inductor does not run away under

any circumstance (even with VOUT near 0V).

Negative Current Limit

If an external source somehow drives current into VOUT, the

controller attempts to regulate VOUT by reversing its inductor

current to absorb the externally sourced current. If the external

source is low impedance, the current may be reversed to

unacceptable levels and the controller initiates its negative

current limit protection. Similar to normal overcurrent, the

negative current protection is realized by monitoring the current

through the lower FET. When the valley point of the inductor

current reaches negative current limit, the lower FET is turned off

and the upper FET is forced on until current reaches the Positive

current limit or an internal clock signal is issued. At this point, the

lower FET is allowed to operate. If the current is pulled to the

negative limit again on the next cycle, the upper FET is forced on

again and the current is forced to 1/6th of the positive current

limit. Next, the controller turns off both FETs and waits for COMP

to indicate a return to normal operation. During this time, the

controller applies a 100Ω load from PHASE to PGND and

attempts to discharge the output. Negative current limit is a

pulse-by-pulse style operation and recovery is automatic.

Over-Temperature Protection

Over-temperature protection limits maximum junction

temperature in the ISL854102. When junction temperature (TJ)

exceeds +150°C, both FETs are turned off and the controller

waits for the temperature to decrease by approximately 20°C.

During this time PG is pulled low. When temperature is within an

acceptable range, the controller initiates a normal soft-start

sequence. For continuous operation, do not exceed the +125°C

junction temperature rating.

Boot Undervoltage Protection

If the boot capacitor voltage falls below 1.8V, the boot

undervoltage protection circuit turns on the lower FET for 400ns

to recharge the capacitor. This operation may arise during long

periods of no switching such as PFM no load situations. In PWM

operation near dropout (VIN near VOUT), the regulator can hold

the upper FET on for multiple clock cycles. To prevent the boot

capacitor from discharging, the lower FET is forced on for

approximately 200ns every 10 clock cycles.

Application Guidelines

Simplifying the Design

While the ISL854102 offers user programmed options for most

parameters, the easiest implementation with fewest

components involves selecting internal settings for SS, COMP,

and FS. Table 1 on page 4 provides component value selections

for a variety of output voltages and allows you to implement

solutions with a minimum of effort.

Operating Frequency

The ISL854102 operates at a default switching frequency of

500kHz if the FS pin is tied to VCC. Tie a resistor from the FS pin

to GND to program the switching frequency from 300kHz to

2MHz, as shown in Equation 4.

Where:

t is the switching period in µs.

Minimum On/Off-Time Limitation

Minimum on-time (tMIN_ON) is the shortest duration of time that

the HS FET can be turned on and minimum off time (tMIN_OFF) is

the shortest duration of time that the HS FET can be turned off.

The typical tMIN_ON is 90ns and the typical tMIN_OFF is 150ns.

For a given tMIN_ON and tMIN_OFF, a higher switching frequency

results in a narrower range of allowed duty cycle, which

translates to a smaller allowed VIN range.

For a given output voltage (VOUT) and switching frequency (fSW),

the maximum allowed voltage is given by (Equation 5):

The minimum allowed voltage is given by (Equation 6):

RFS k



108.75k

 t



0.2

s  1s



–

(EQ. 4)

FIGURE 35. RFS SELECTION vs fSW

300

200

100

500

750

1000

1250

1500

1750

2000

fSW (kHz)

400

250

VIN max



VOUT

fSW tMIN_ON



---------------------------------------

(EQ. 5)

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