ISL854102

FN8870 Rev.1.00

Page 3 of 21

Mar 15, 2019

Pin Configuration

12 LD 4x3 DFN

TOP VIEW

VCC

EN

VIN

FB

PHASE

BOOT

COMP

1

2

3

4

5

12

11

10

9

8

PG

SS

FS

PGND 6

GND

7

SYNC

Pin Descriptions

PIN NUMBER

SYMBOL

PIN DESCRIPTION

1

SS

Controls the soft-start ramp time of the output. A single capacitor from the SS pin to ground determines the

output ramp rate. See “Soft-Start” on page 13 for soft-start details. If the SS pin is tied to VCC, an internal

soft-start of 2ms is used.

2

SYNC

Synchronization and light load operational mode selection input. Connect to logic high or VCC for PWM

mode. Connect to logic low or ground for PFM mode. Logic ground enables the IC to automatically choose

PFM or PWM operation. Connect to an external clock source for synchronization with positive edge trigger.

The sync source must be higher than the programmed IC frequency. An internal 5MΩ pull-down resistor

prevents an undefined logic state if SYNC is left floating.

3

BOOT

Floating bootstrap supply pin for the power MOSFET gate driver. The bootstrap capacitor provides the

necessary charge to turn on the internal N-Channel MOSFET. Connect an external 100nF capacitor from this

pin to PHASE.

4

VIN

The input supply for the power stage of the regulator and the source for the internal linear bias regulator.

Place a minimum of 4.7µF ceramic capacitance from VIN to GND and close to the IC for decoupling.

5

PHASE

Switch node output. It connects the switching FETs with the external output inductor.

6

PGND

Power ground connection. Connect directly to the system GND plane.

7

EN

Regulator enable input. The regulator and bias LDO are held off when the pin is pulled to ground. When the

voltage on this pin rises above 1V, the chip is enabled. Connect this pin to VIN for automatic start-up. Do not

connect the EN pin to VCC because the LDO is controlled by EN voltage.

8

PG

Open-drain, power-good output that is pulled to ground when the output voltage is below regulation limits or

during the soft-start interval. There is an internal 5MΩ internal pull-up resistor.

9

VCC

Output of the internal 5V linear bias regulator. Decouple to PGND with a 1µF ceramic capacitor at the pin.

10

FB

Feedback pin for the regulator. FB is the inverting input to the voltage loop error amplifier. COMP is the

output of the error amplifier. The output voltage is set by an external resistor divider connected to FB. In

addition, the PWM regulator’s power-good and UVLO circuits use FB to monitor the regulator output voltage.

11

COMP

COMP is the output of the error amplifier. When it is tied to VCC, internal compensation is used. When only

an RC network is connected from COMP to GND, external compensation is used. See “Loop Compensation

Design” on page 16 for more details.

12

FS

Frequency selection pin. Tie to VCC for 500kHz switching frequency. Connect a resistor to GND for adjustable

frequency from 300kHz to 2MHz.

EPAD

GND

Signal ground connections. Connect to the application board GND plane with at least five vias. All voltage

levels are measured with respect to this pin. The EPAD MUST NOT float.