NET2272 datasheet(29/102 Pages) ETC2

29 / 102 page

Specification

NET2272 USB Peripheral Controller

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 NetChip Technology, Inc., 2003

Patent Pending

335 Pioneer Way, Mountain View, California 94041

TEL (650) 526-1490

FAX (650) 526-1494

http://www.netchip.com

Rev 1.2, October 15, 2003

4.6.3 DMA Split Bus Mode

In this mode, the external DMA controller is connected to LD[15:8] of the data bus, while the local CPU is

connected to LD[7:0] of the data bus. The DMA Split Bus Mode bit of the LOCCTL register enables DMA split

Bus Mode.

The split mode DMA transactions are the same as normal DMA transactions, except that DMARD# is used instead

of IOR#, and DMAWR# is used instead of IOW#. While DMA transactions are taking place using LD[15:8], the

local CPU can simultaneously access configuration registers for any endpoint, and can access endpoint buffers not

involved with the DMA.

4.6.4 Terminating DMA Transfers

The EOT signal is used to halt a DMA transfer, and is typically provided by an external DMA controller. It should

be asserted while DACK (and optionally IOR#, IOW#, DMARD#, or DMAWR#) are simultaneously active to

indicate that DMA activity has stopped. Although an EOT signal indicates that DMA has terminated, the USB

transfer (in the case of an IN transaction) is not complete until the last byte has been transferred from the endpoint’s

buffer to the USB. The EOT input resets the NET2272 DMA Request Enable bit of the DMAREQ register. When

EOT is detected, the current endpoint buffer is automatically validated, causing any remaining data in the current

packet to be sent to the host as a short packet. If there is no data in the buffer when the current buffer is validated,

then a zero length packet will be returned in response to the next IN token. The DMA Request Enable bit is also

automatically cleared when the EP_TRANSFER counter reaches zero for IN endpoints or when the local CPU

writes a 0 to the EP_TRANSFER counter.

If the external DMA controller doesn’t provide an EOT signal, the local CPU can terminate the DMA transfer at any

time by resetting the NET2272 DMA Request Enable bit. If the NET2272 DMA Request Enable bit is cleared

during the middle of a DMA cycle (only possible if using DMA split mode), the current cycle will complete before

DMA requests are terminated. The endpoint buffer is not automatically validated when the DMA Request Enable is

cleared. In this case, the CPU needs to explicitly validate the packet by writing a zero to the EP_TRANSFER

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