IS25WP064A-RBLE datasheet(12/111 Pages) ISSI

12 / 111 page

IS25WP064A/032A

Integrated Silicon Solution, Inc.- www.issi.com

Rev. 00D

03/01/2016

4. SPI MODES DESCRIPTION

Multiple IS25WP064A/032A devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e.

microcontroller, as shown in Figure 4.1. The devices support either of two SPI modes:

Mode 0 (0, 0)

Mode 3 (1, 1)

The difference between these two modes is the clock polarity. When the SPI master is in stand-by mode, the

serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer

to Figure 4.2 and Figure 4.3 for SPI and QPI mode. In both modes, the input data is latched on the rising edge of

Serial Clock (SCK), and the output data is available from the falling edge of SCK.

Figure 4.1 Connection Diagram among SPI Master and SPI Slaves (Memory Devices)

Notes:

1. In case of 16-pin SOIC and 24-ball TFBGA, dedicated RESET# can be supported without sharing with HOLD# pin

for the dedicated parts. See the Ordering Information for the dedicated RESET# option.

2. SI and SO pins become bidirectional IO0 and IO1 respectively during Dual I/O mode and SI, SO, WP#, and HOLD#

pins become bidirectional IO0, IO1, IO2, and IO3 respectively during Quad I/O or QPI mode.

SPI interface with

(0,0) or (1,1)

SPI Master

(i.e. Microcontroller)

SPI

Memory

Device

SPI

Memory

Device

SPI

Memory

Device

SCK SO

SCK

SDI

SDO

CE#

WP#

HOLD# or

RESET

SCK SO

CE#

WP# HOLD# or

RESET#

SCK SO

CE#

WP#

CS3

CS2

CS1

HOLD# or

RESET#

IS25WP064A-RBLE Datasheet(PDF) 12 Page - Integrated Silicon Solution, Inc

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