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USB3370 Datasheet(PDF) 55 Page - Microchip Technology |
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USB3370 Datasheet(HTML) 55 Page - Microchip Technology |
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55 / 75 page  2012 - 2015 Microchip Technology Inc. DS00001915B-page 55 USB3370 7.1.1.10 USB Interrupt Status Address = 13h (read only) This register dynamically updates to reflect current status of interrupt sources. 7.1.1.11 USB Interrupt Latch Address = 14h (read only with auto clear) Note 7-2 rd: Read Only with auto clear. IdGnd Fall 4 rd/w/s/c 1b Generate an interrupt event notification when IdGnd changes from high to low. Reserved 7:5 rd 0h Read only, 0. Field Name Bit Access Default Description HostDisconnect 0 rd (read only) 0b Current value of the UTMI+ HS Hostdisconnect output. Applicable only in host mode. VbusValid 1 0b Current value of the UTMI+ Vbusvalid output. If VbusValid Rise and VbusValid Fall are set this register will read 0. SessValid 2 0b Current value of the UTMI+ SessValid output. This register will always read the current status of the Session Valid comparator regardless of the SessValid Rise and SessValid Fall settings. SessEnd 3 0b Current value of the UTMI+ SessEnd output. If SessEnd Rise and SessEnd Fall are set this register will read 0. IdGnd 4 0b Current value of the UTMI+ IdGnd output. Reserved 7:5 0h Read only, 0. Note: The default value is only valid after POR. When the register is read it will match the current status of the comparators at the moment the register is read. Field Name Bit Access Default Description HostDisconnect Latch 0 rd (Note 7-2) 0b Set to 1b by the PHY when an unmasked event occurs on Hostdisconnect. Cleared when this register is read. Applicable only in host mode. VbusValid Latch 1 0b Set to 1b by the PHY when an unmasked event occurs on VbusValid. Cleared when this register is read. SessValid Latch 2 0b Set to 1b by the PHY when an unmasked event occurs on SessValid. Cleared when this register is read. SessEnd Latch 3 0b Set to 1b by the PHY when an unmasked event occurs on SessEnd. Cleared when this register is read. IdGnd Latch 4 0b Set to 1b by the PHY when an unmasked event occurs on IdGnd. Cleared when this register is read. Reserved 7:5 rd 0h Read only, 0. Field Name Bit Access Default Description |
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