ADP5589ACBZ-02-R7 datasheet(23/52 Pages) AD

Part #	ADP5589ACBZ-02-R7

Description	Keypad Decoder and I/O Expansion

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Manufacturer	AD [Analog Devices]

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Data Sheet

ADP5589

Rev. B | Page 23 of 52

DETAILED REGISTER DESCRIPTIONS

Note: N/A throughout this section means not applicable.

Note: All registers default to 0000 0000 unless otherwise specified.

ID Register 0x00

Table 7. ID Bit Descriptions

Bits

Name

R/W

Description

[7: 4]

MAN_ID

R

Manufacturer ID, default = 0001.

[3:0]

REV_ID

R

Rev ID.

Default = 0001 XXXX

INT_STATUS Register 0x01

Table 8. INT_STATUS Bit Descriptions

Bits

Name

R/W

Description

[7: 6]

N/A

Reserved.

5

LOGIC2_INT

R/W

0 = no interrupt.

1 = interrupt due to a general Logic 2 condition.

Write a 1 to this bit to clear it.

4

LOGIC1_INT

R/W

0 = no interrupt.

1 = interrupt due to a general Logic 1 condition.

Write a 1 to this bit to clear it.

3

LOCK_INT

R/W

0 = no interrupt.

1 = interrupt due to a lock/unlock condition.

The user can read LOCK_STAT (0x02[5]) to determine if LOCK_INT is due to a lock or unlock event.

If LOCK_STAT = 1, LOCK_INT is due to a lock event.

If LOCK_STAT = 0, LOCK_INT is due to an unlock event.

Write a 1 to this bit to clear it.

If lock mode is enabled via the software bit LOCK_EN (0x37[0]), a LOCK_INT is not generated

because the processor knows it just enabled lock mode.

If lock mode is disabled (while locked) via the software bit LOCK_EN, a LOCK_INT is not generated

because the processor knows it just disabled lock mode.

2

OVRFLOW_INT

R/W

0 = no interrupt.

1 = interrupt due to an overflow condition.

Write a 1 to this bit to clear it.

1

GPI_INT

R/W

0 = no interrupt.

1 = interrupt due to a general GPI condition.

This bit is not set by a GPI that has been configured to update the FIFO and event count.

Write a 1 to this bit to clear it.

This bit cannot be cleared until all GPI_x_INT bits are cleared.

0

EVENT_INT

R/W

0 = no interrupt.

1 = interrupt due to key event (press/release), GPI event (GPI programmed for FIFO updates), or

Logic 1/Logic 2 event (programmed for FIFO updates).Write a 1 to this bit to clear it.

Status Register 0x02

Table 9. Status Bit Descriptions

Bits

Name

R/W

Description

7

LOGIC2_STAT

R

0 = output from Logic Block 2. (LY2) is low.

1 = output from Logic Block 2. (LY2) is high.

6

LOGIC1_STAT

R

0 = output from Logic Block 1 (LY1) is low.

1 = output from Logic Block 1 (LY1) is high.

5

LOCK_STAT

R

0 = unlocked.

1 = locked.

[4:0]

EC[4:0]

R

Event count value. Indicates how many events are currently stored on the FIFO.

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