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ADP5589ACBZ-02-R7 Datasheet(PDF) 19 Page - Analog Devices |
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ADP5589ACBZ-02-R7 Datasheet(HTML) 19 Page - Analog Devices |
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19 / 52 page  Data Sheet ADP5589 Rev. B | Page 19 of 52 REGISTER INTERFACE Register access of the ADP5589 is acquired via its I2C-compatible serial interface. The interface can support clock frequencies of up to 1 MHz. If the user is accessing the FIFO or key event counter (KEC), FIFO/KEC updates are paused. If the clock frequency is very low, events may not be recorded in a timely manner. FIFO or KEC updates can happen up to 23 μs after an interrupt is asserted because of the number of I2C cycles required to perform an I2C read or write. This delay should not present an issue to the user. Figure 27 shows a typical write sequence for programming an internal register. The cycle begins with a start condition, followed by the hard coded 7-bit device address, which for the ADP5589 is 0x34, followed by the R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. The data byte to be written is sent next. The ADP5589 acknowledges the data byte by pulling the data line low. A stop condition completes the sequence. Figure 28 shows a typical multibyte write sequence for program- ming internal registers. The cycle begins with a start condition followed by the 7-bit device address (0x34), followed by the R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register to which data is to be written is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. The data byte to be written is sent next. The ADP5589 acknowledges the data byte by pulling the data line low. The pointer address is then incremented to write the next data byte, until it finishes writing the n data byte. The ADP5589 pulls the data line low after every byte, and a stop condition completes the sequence. Figure 29 shows a typical byte read sequence for reading internal registers. The cycle begins with a start condition followed by the 7-bit device address (0x34), followed by the R/W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The address of the register from which data is to be read is sent next. The ADP5589 acknowledges the register pointer byte by pulling the data line low. A start condi- tion is repeated, followed by the 7-bit device address (0x34), followed by the R/W bit set to 1 for a read cycle. The ADP5589 acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The host pulls the data line high (no acknowledge), and a stop condition completes the sequence. START 0 = WRITE 7-BIT DEVICE ADDRESS ADP5589 ACK 8-BIT REGISTER POINTER 8-BIT WRITE DATA 00 0 0 ADP5589 ACK ADP5589 ACK STOP Figure 27. I2C Single-Byte Write Sequence START 0 = WRITE 7-BIT DEVICE ADDRESS ADP5589 ACK 8-BIT REGISTER POINTER WRITE BYTE 1 WRITE BYTE 2 WRITE BYTE n 00 0 0 0 0 0 ADP5589 ACK ADP5589 ACK ADP5589 ACK ADP5589 ACK ADP5589 ACK STOP Figure 28. I2C Multibyte Write Sequence START 0 = WRITE 7-BIT DEVICE ADDRESS 7-BIT DEVICE ADDRESS ADP5589 ACK 8-BIT REGISTER POINTER 8-BIT READ DATA 00 0 1 0 1 REPEAT START 1 = READ ADP5589 ACK ADP5589 ACK NO ACK STOP Figure 29. I2C Single-Byte Read Sequence |
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