AD5318 datasheet(19/28 Pages) AD

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AD5308/AD5318/AD5328

Rev. F | Page 19 of 28

MICROPROCESSOR INTERFACE

ADSP-2101/ADSP-2103-to-

AD5308/AD5318/AD5328 INTERFACE

Figure 36 shows a serial interface between the AD5308/AD5318/

AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/

ADSP-2103 should be set up to operate in the SPORT transmit

alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is

programmed through the SPORT control register and should be

configured as follows: internal clock operation, active low framing,

and 16-bit word length. Transmission is initiated by writing a word

to the Tx register after the SPORT has been enabled. The data is

clocked out on each rising edge of the DSP’s serial clock and

clocked into the AD5308/AD5318/ AD5328 on the falling edge

of the DAC’s SCLK.

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS

AD5308/

AD5318/

AD5328*

SYNC

SCLK

DIN

Figure 36. ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface

68HC11/68L11-to-AD5308/AD5318/AD5328

INTERFACE

Figure 37 shows a serial interface between the AD5308/AD5318/

AD5328 and the 68HC11/68L11 microcontroller. SCK of the

68HC11/68L11 drives the SCLK of the AD5308/AD5318/AD5328,

and the MOSI output drives the serial data line (DIN) of the DAC.

The sync signal is derived from a port line (PC7). The set up

conditions for the correct operation of this interface are as follows:

the 68HC11/68L11 should be configured so that its CPOL bit is a

0 and its CPHA bit is a 1. When data is being transmitted to the

DAC, the sync line is taken low (PC7). When the 68HC11/ 68L11

is configured as just described, data appearing on the MOSI output

is valid on the falling edge of SCK. Serial data from the 68HC11/

68L11 is transmitted in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. Data is transmitted MSB

first. To load data to the AD5308/AD5318/AD5328, PC7 is left

low after the first eight bits are transferred, and a second serial

write operation is performed to the DAC. PC7 is taken high at

the end of this procedure.

68HC11/68L11

*ADDITIONAL PINS OMITTED FOR CLARITY

PC7

AD5308/

AD5318/

AD5328*

SYNC

MOSI

SCK

DIN

SCLK

Figure 37. 68HC11/68L11-to-AD5308/AD5318/ AD5328 Interface

80C51/80L51-to-AD5308/AD5318/AD5328

INTERFACE

Figure 38 shows a serial interface between the AD5308/AD5318/

AD5328 and the 80C51/80L51 microcontroller. The setup for

the interface is as follows: TxD of the 80C51/80L51 drives SCLK

of the AD5308/AD5318/AD5328, while RxD drives the serial data

line of the part. The SYNC signal is again derived from a bit

programmable pin on the port. In this case, port line P3.3 is used.

When data is transmitted to the AD5308/AD5318/AD5328, P3.3

is taken low. The 80C51/80L51 transmits data only in 8-bit bytes;

thus, only eight falling clock edges occur in the transmit cycle. To

load data to the DAC, P3.3 is left low after the first eight bits are

transmitted, and a second write cycle is initiated to transmit the

second byte of data. P3.3 is taken high following the completion

of this cycle. The 80C51/80L51 outputs the serial data in a format

that has the LSB first. The AD5308/AD5318/AD5328 requires

its data with the MSB as the first bit received. The 80C51/80L51

transmit routine should take this into account.

80C51/80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY

P3.3

AD5308/

AD5318/

AD5328*

SYNC

RxD

TxD

DIN

SCLK

Figure 38. 80C51/80L51-to-AD5308/AD5318/AD5328 Interface

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