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AD5308/AD5318/AD5328

Rev. F | Page 16 of 28

POWER-ON RESET

The AD5308/AD5318/AD5328 are provided with a power-on

reset function so that they power up in a defined state. The

power-on state is

•

Normal operation

•

Reference inputs unbuffered

•

0 V to VREF output range

•

Output voltage set to 0 V

•

LDAC bits set to LDAC high

Both input and DAC registers are filled with 0s and remain so

until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

POWER-DOWN MODE

The AD5308/AD5318/AD5328 have low power consumption,

typically dissipating 2.4 mW with a 3 V supply and 5 mW with

a 5 V supply. Power consumption can be further reduced when

the DACs are not in use by putting them into power-down

mode, which is described in the Serial Interface section.

When in default mode, all DACs work normally with a typical

power consumption of 1 mA at 5 V (800 μA at 3 V). However,

when all DACs are powered down, that is, in power-down

mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V).

Not only does the supply current drop, but the output stage is

also internally switched from the output of the amplifier,

making it open-circuit. This has the advantage that the output is

three-state while the part is in power-down mode, and provides

a defined input condition for whatever is connected to the

output of the DAC amplifier. The output stage is illustrated in

Figure 31.

The bias generator, the output amplifiers, the resistor string, and

all other associated linear circuitry are shut down when the

power-down mode is activated. However, the contents of the

registers are unaffected when in power-down. In fact, it is

possible to load new data to the input registers and DAC regis-

ters during power-down. The DAC outputs update as soon as

the device comes out of power-down mode. The time to exit

power-down is typically 2.5 μs when VDD = 5 V and 5 μs when

VDD = 3 V.

POWER-DOWN

CIRCUITRY

RESISTOR-

STRING DAC

AMPLIFIER

VOUT

Figure 31. Output Stage During Power-Down

SERIAL INTERFACE

The AD5308/AD5318/AD5328 are controlled over a versatile

3-wire serial interface that operates at clock rates up to 30 MHz

and is compatible with SPI, QSPI, MICROWIRE, and DSP

interface standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the

device as a 16-bit word under the control of a serial clock input,

SCLK. The timing diagram for this operation is shown in Figure 2.

The SYNC input is a level-triggered input that acts as a frame

synchronization signal and chip enable. Data can be transferred

into the device only while SYNC is low. To start the serial data

transfer, SYNC should be taken low, observing the minimum

SYNC to SCLK falling edge set-up time, t4. After SYNC goes

low, serial data is shifted into the device’s input shift register on

the falling edges of SCLK for 16 clock pulses.

To end the transfer, SYNC must be taken high after the falling

edge of the 16th SCLK pulse, observing the minimum SCLK

falling edge to SYNC rising edge time, t7.

After the end of the serial data transfer, data is automatically

transferred from the input shift register to the input register of

the selected DAC. If SYNC is taken high before the 16th falling

edge of SCLK, the data transfer is aborted and the DAC input

registers are not updated.

Data is loaded MSB first (Bit 15). The first bit determines

whether it is a DAC write or a control function.

DAC Write

The 16-bit word consists of 1 control bit and 3 address bits fol-

lowed by 8, 10, or 12 bits of DAC data, depending on the device

type. In the case of a DAC write, the MSB is a 0. The next 3

address bits determine whether the data is for DAC A, DAC B,

DAC C, DAC D, DAC E, DAC F, DAC G, or DAC H. The

AD5328 uses all 12 bits of DAC data. The AD5318 uses 10 bits

and ignores the 2 LSBs. The AD5308 uses 8 bits and ignores the

last 4 bits. These ignored LSBs should be set to 0. The data

format is straight binary, with all 0s corresponding to 0 V

output and all 1s corresponding to full-scale output.

Table 6. Address Bits for the AD5308/AD5318/AD5328

A2 (Bit 14)

A1 (Bit 13)

A0 (Bit 12)

DAC Addressed

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

DAC G

DAC H

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