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AD5308/AD5318/AD5328

Rev. F | Page 18 of 28

Power-Down Mode

The individual channels of the AD5308/AD5318/AD5328 can

be powered down separately. The control mode for this is (10).

On completion of this write sequence, the channels that have

been set to 1 are powered down.

Reset Mode

This mode consists of two possible reset functions, as outlined

in Table 9.

Table 9. Reset Mode

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11 ... 0

Description

x ... x

DAC data reset

x ... x

Data and control reset

DAC Data Reset: On completion of this write sequence, all

DAC registers and input registers are filled with 0s.

Data and Control Reset: This function carries out a DAC data

reset and resets all the control bits (GAIN, BUF, VDD, LDAC, and

power-down channels) to their power-on conditions.

LOW POWER SERIAL INTERFACE

To minimize the power consumption of the device, the interface

powers up fully only when the device is being written to, that is,

on the falling edge of SYNC. The SCLK and DIN input buffers

are powered down on the rising edge of SYNC.

LOAD DAC INPUT (LDAC) FUNCTION

Access to the DAC registers is controlled by both the LDAC pin

and the LDAC mode bits. The operation of the LDAC function

can be likened to the configuration shown in

Figure 35

LDAC FUNCTION

EXTERNAL LDAC PIN

INTERNAL LDAC MODE

Figure 35. LDAC Function

If the user wishes to update the DAC through software, the

LDAC pin should be tied high and the LDAC mode bits set as

required. Alternatively, if the user wishes to control the DAC

through hardware, that is, the LDAC pin, the LDAC mode bits

should be set to LDAC high (default mode).

Use of the LDAC function enables double-buffering of the DAC

data, and the GAIN, BUF and VDD bits. There are two ways in

which the LDAC function can operate:

Synchronous LDAC: The DAC registers are updated after new

data is read in on the falling edge of the 16th SCLK pulse.

LDAC can be permanently low or pulsed as in

Figure 2

Asynchronous LDAC: The outputs are not updated at the same

time that the input registers are written to. When LDAC goes

low, the DAC registers are updated with the contents of the

input register.

DOUBLE-BUFFERED INTERFACE

The AD5308/AD5318/AD5328 DACs all have double-buffered

interfaces consisting of two banks of registers: input and DAC.

The input registers are connected directly to the input shift

registers contain the digital code used by the resistor strings.

When the LDAC pin is high and the LDAC bits are set to (01),

the DAC registers are latched and the input registers can change

state without affecting the contents of the DAC registers. How-

ever, when the LDAC bits are set to (00) or when the LDAC pin

is brought low, the DAC registers become transparent and the

contents of the input registers are transferred to them.

The double-buffered interface is useful if the user requires

simultaneous updating of all DAC outputs. The user can write

up to seven of the input registers individually and then, by

bringing LDAC low when writing to the remaining DAC input

These parts contain an extra feature whereby a DAC register is

not updated unless its input register has been updated since the

last time LDAC was low. Normally, when LDAC is brought low,

the DAC registers are filled with the contents of the input regis-

ters. In the case of the AD5308/AD5318/AD5328, the part

updates the DAC register only if the input register has been

changed since the last time the DAC register was updated,

thereby removing unnecessary digital crosstalk.

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