CC1150-RTY1 datasheet(22/67 Pages) TI

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CC1150

SWRS037A

Page 22 of 60

10.6

PATABLE Access

The 0x3E address is used to access the

PATABLE

, which is used for selecting PA

power control settings. The SPI expects up to

eight data bytes after receiving the address.

By programming the PATABLE, controlled PA

power ramp-up and ramp-down can be

achieved, as well as ASK modulation shaping

for reduced bandwidth. Note that the ASK

modulation shaping is limited to output powers

below -1 dBm. See SmartRF Studio [11] for

recommended shaping sequence. See also

section 21 on page 35 for details on output

power programming.

The PATABLE is an 8-byte table that defines

the PA control settings to use for each of the

eight PA power values (selected by the 3-bit

value FREND0.PA_POWER). The table is

written and read from the lowest setting (0) to

the highest (7), one byte at a time. An index

counter is used to control the access to the

table. This counter is incremented each time a

byte is read or written to the table, and set to

the lowest index when CSn is high. When the

highest value is reached the counter restarts at

zero.

The access to the PATABLE is either single

byte or burst access depending on the burst

bit. When using burst access the index counter

will count up; when reaching 7 the counter will

restart at 0. The read/write bit controls whether

the access is a write access (R/W=0) or a read

access (R/W=1).

If one byte is written to the PATABLE and this

value is to be read out then CSn must be set

high before the read access in order to set the

index counter back to zero.

Note that the content of the PATABLE is lost

when entering the SLEEP state. For more

information, see DN501 [8].

11 Microcontroller Interface and Pin Configuration

In a typical system,

CC1150 will interface to a

microcontroller. This microcontroller must be

able to:

• Program

CC1150 into different modes,

• Write buffered data

• Read back status information via the 4-wire

SPI-bus configuration interface (SI, SO,

SCLK

and CSn).

11.1

Configuration Interface

The microcontroller uses four I/O pins for the

SPI configuration interface (SI, SO, SCLK and

CSn

). The SPI is described in Section 10 on

page 18.

11.2

General Control and Status Pins

The

CC1150 has one dedicated configurable pin

(GDO0) and one shared pin (GDO1/SO) that

can output internal status information useful for

control software. These pins can be used to

generate interrupts on the MCU. See section

22 page 37 for more details of the signals that

can be programmed. The shared pin is the SO

pin in the SPI interface. The default setting for

GDO1/SO

is 3-state output. By selecting any

other

the

programming

options

the

GDO1/SO

pin will become a generic pin. When

CSn

is low, the pin will always function as a

normal SO pin.

In the synchronous and asynchronous serial

modes, the GDO0 pin is used as a serial TX

data input pin while in transmit mode.

The GDO0 pin can also be used for an on-chip

analog temperature sensor. By measuring the

voltage on the GDO0 pin with an external ADC,

the

temperature

can

calculated.

Specifications for the temperature sensor are

found in section 4.5 on page 9. With default

PTEST

sensor output is only available when the

frequency synthesizer is enabled (e.g. the

MANCAL, FSTXON and TX states).

It is

necessary to write 0xBF to the PTEST register

to use the analog temperature sensor in the

IDLE state. Before leaving the IDLE state, the

PTEST

default value (0x7F).

CC1150-RTY1 Datasheet(PDF) 22 Page - Texas Instruments

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