CC1150-RTY1 datasheet(35/67 Pages) TI

35 / 67 page

CC1150

SWRS037A

Page 35 of 60

20 Voltage Regulators

CC1150 contains several on-chip linear voltage

regulators, which generate the supply voltage

needed by

low-voltage

modules. These

voltage regulators are invisible to the user, and

can be viewed as integral parts of the various

modules. The user must however make sure

that the absolute maximum ratings and

required pin voltages in Table 1 and Table 11

are not exceeded.

Setting the CSn pin low turns on the voltage

regulator to the digital core and start the

crystal oscillator. The SO pin on the SPI

interface must go low before the first positive

edge on the SCLK (setup time is s given in

Table 15).

If the chip is programmed to enter power-down

mode (SPWD strobe issued), the power will be

turned off after CSn goes high. The power and

crystal oscillator will be turned on again when

CSn

goes low.

The voltage regulator for the digital core

requires one external decoupling capacitor.

The voltage regulator output should only be

used for driving the

CC1150.

21 Output Power Programming

The RF output power level from the device has

two levels of programmability, as illustrated in

Figure 21. Firstly, the special PATABLE

output power settings. Secondly, the 3-bit

FREND0.PA_POWER

value

selects

the

PATABLE

entry

use.

This

two-level

functionality provides flexible PA power ramp

up and ramp down at the start and end of

transmission, as well as ASK modulation

shaping. In each case, all the PA power

settings in the PATABLE from index 0 up to the

FREND0.PA_POWER

value are used.

The power ramping at the start and at the end

of a packet can be turned off by setting

FREND0.PA_POWER

zero

and

then

programming the desired output power to

index 0 in the PATABLE.

If OOK modulation is used, the logic 0 and

logic 1 power levels shall be programmed to

index 0 and 1 respectively.

Table 22 contains recommended PATABLE

settings

for

various

output

levels

and

frequency bands. DN012 [3] gives complete

tables for the different frequency bands. Using

PA settings from 0x61 to 0x6F is not

recommended. Table 23 contains output

power and current consumption for default

PATABLE setting (0xC6).

PATABLE

must be programmed in burst mode

if you want to write to other entries than

PATABLE[0].

See section 10.6 on page 22

for PATABLE programming details.

e.g 6

PA_POWER[2:0]

in FREND0 register

PATABLE(0)[7:0]

PATABLE(1)[7:0]

PATABLE(2)[7:0]

PATABLE(3)[7:0]

PATABLE(4)[7:0]

PATABLE(5)[7:0]

PATABLE(6)[7:0]

PATABLE(7)[7:0]

Index into PATABLE(7:0)

The PA uses this

setting.

Settings 0 to PA_POWER are

used during ramp-up at start of

transmission and ramp-down at

end of transmission, and for

ASK/OOK modulation.

The SmartRF® Studio software

should be used to obtain optimum

PATABLE settings for various

output powers.

Figure 21: PA_POWER and PATABLE

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