CC1150-RTY1 datasheet(19/67 Pages) TI

19 / 67 page

CC1150

SWRS037A

Page 19 of 60

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

Hi-Z

Figure 9: Configuration Registers Write and Read Operations

Parameter

Description

Min

Max

Units

SCLK

frequency

100 ns delay inserted between address byte and data byte (single access), or between

address and data, and between each data byte (burst access).

MHz

SCLK

frequency, single access

No delay between address and data byte

fSCLK

SCLK

frequency, burst access

No delay between address and data byte, or between data bytes

6.5

tsp,pd

CSn

low to positive edge on SCLK, in power-down mode

150

µs

tsp

CSn

low to positive edge on SCLK, in active mode

tch

Clock high

tcl

Clock low

trise

Clock rise time

tfall

Clock fall time

Single access

tsd

Setup data (negative SCLK edge) to

positive edge on SCLK

(tsd applies between address and data bytes, and

between data bytes)

Burst access

thd

Hold data after positive edge on SCLK

tns

Negative edge on SCLK to CSn high

Table 15: SPI Interface Timing Requirements

Note that the minimum tsp,pd figure in Table 15 can be used in cases where the user does not read the

CHIP_RDYn

signal. CSn low to positive edge on SCLK when the chip is woken from power-down

depends on the start-up time of the crystal being used. The 150 µs in Table 15 is the crystal oscillator

start-up time measured using crystal AT-41CD2 from NDK.

10.1

Chip Status Byte

When the header byte, data byte or command

strobe is sent on the SPI interface, the chip

status byte is sent by the

CC1150 on the SO pin.

The status byte contains key status signals,

useful for the MCU. The first bit, s7, is the

CHIP_RDYn

signal; this signal must go low

before the first positive edge of SCLK. The

CHIP_RDYn

signal indicates that the crystal is

running and the regulated digital supply

voltage is stable.

Bit 6, 5 and 4 comprises the STATE value. This

value reflects the state of the chip. The XOSC

and power to the digital core is on in the IDLE

state, but all other modules are in power down.

The frequency and channel configuration

should only be updated when the chip is in this

state. The TX state will be active when the

chip is transmitting.

The last four bits (3:0) in the status byte con-

tains FIFO_BYTES_AVAILABLE. This field

CC1150-RTY1 Datasheet(PDF) 19 Page - Texas Instruments

CC1150-RTY1 Datasheet(HTML) 19 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67

Datasheet Download

Link URL