EP1M350 datasheet(3/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Tables 2 and 3 show the MercuryTM FineLine BGATM device package sizes,

options, and I/O pin counts.

General

Description

Mercury devices integrate high-speed differential transceivers and

support for CDR with a speed-optimized PLD architecture. These

transceivers are implemented through the dedicated serializer,

deserializer, and clock recovery circuitry in the HSDI and incorporate

support for the LVDS, LVPECL, and 3.3-V PCML I/O standards. This

circuitry, together with enhanced I/O elements (IOEs) and support for

numerous I/O standards, allows Mercury devices to meet high-speed

interface requirements.

Mercury devices are the first PLDs optimized for core performance. These

LUT-based, enhanced memory devices use a network of fast routing

resources to achieve optimal performance. These resources are ideal for

data-path, register-intensive, mathematical, digital signal processing

(DSP), or communications designs.

Table 2. Mercury Package Sizes

Feature

484-Pin

FineLine BGA

780-Pin

FineLine BGA

Pitch (mm)

1.00

Area (mm2)529

841

Length

× width (mm × mm)

× 23

× 29

Table 3. Mercury Package Options & I/O Count

Device

484-Pin

FineLine BGA

780-Pin

FineLine BGA

EP1M120

303

EP1M350

486

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