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EP1M350 Datasheet(PDF) 2 Page - Altera Corporation

Part # EP1M350
Description  Programmable Logic Device Family
PDF  86 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP1M350 Datasheet(HTML) 2 Page - Altera Corporation

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Altera Corporation
Mercury Programmable Logic Device Family Data Sheet
...and More
Features
■
Advanced high-speed I/O features
–
Robust I/O standard support, including LVTTL, PCI up to
66 MHz, 3.3-V AGP in 1
× and 2× modes, 3.3-V SSTL-3 and 2.5-V
SSTL-2, GTL+, HSTL, CTT, LVDS, LVPECL, and 3.3-V PCML
–
High-speed differential interface (HSDI) with dedicated
circuitry for CDR at up to 1.25 Gbps for LVDS, LVPECL, and
3.3-V PCML
–
Support for source-synchronous True-LVDSTM circuitry up to
840 megabits per second (Mbps) for LVDS, LVPECL, and 3.3-V
PCML
–
Up to 18 input and 18 output dedicated differential channels of
high-speed LVDS, LVPECL, or 3.3-V PCML
–
Built-in 100-
Ω termination resistor on HSDI data and clock
differential pairs
–Flexible-LVDSTM circuitry provides 624-Mbps support on up to
100 channels with the EP1M350 device
–
Versatile three-register I/O element (IOE) supporting double
data rate I/O (DDRIO), double data-rate (DDR) SDRAM, zero
bus turnaround (ZBT) SRAM, and quad data rate (QDR) SRAM
■
Designed for low-power operation
–
1.8-V internal supply voltage (VCCINT)
–
MultiVoltTM I/O interface voltage levels (VCCIO) compatible
with 1.5-V, 1.8-V, 2.5-V, and 3.3-V devices
–
5.0-V tolerant with external resistor
■
Advanced interconnect structure
–
Multi-level FastTrack® Interconnect structure providing fast,
predictable interconnect delays
–
Optimized high-speed Priority FastTrack Interconnect for
routing critical paths in a design
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–FastLUTTM connection allowing high speed direct connection
between LEs in the same logic array block (LAB)
–
Leap lines allowing a single LAB to directly drive LEs in adjacent
rows
–
The RapidLAB interconnect providing a high-speed connection
to a 10-LAB-wide region
–
Dedicated clock and control signal resources, including four
dedicated clocks, six dedicated fast global signals, and additional
row-global signals



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