EP1M350 datasheet(21/86 Pages) ALTERA

21 / 86 page

Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

The arithmetic mode also offers clock enable, counter enable, synchronous

up/down control, synchronous clear, and synchronous load options. The

counter enable and synchronous up/down control signals are generated

from the data inputs of the LAB local interconnect. The synchronous clear

and synchronous load options are LAB-wide signals that affect all

registers in the LAB. Consequently, if any of the LEs in a LAB use the

counter mode, other LEs in that LAB must be used as part of the same

counter or be used for a combinatorial function. The Quartus II software

automatically places any registers that are not used by the counter into

other LABs.

Figure 9. Arithmetic Mode LE

Carry-Select Look-Ahead Chain

The CSLA chain provides a very fast carry-forward function between LEs

in arithmetic mode or multiplier mode. The CSLA chain uses the

redundant carry calculation to increase the speed of carry functions. The

LE can calculate sum and carry values for a possible carry-in of 1 and

carry-in of 0 in parallel. The carry-in0 and carry-in1 signals from a

lower-order bit drive forward into the higher-order bit via the parallel

carry chain and feed into both the LUT and the next portion of the CSLA

chain. CSLA chains can begin in any LE within a LAB.

LUT

data1

LAB Carry-In

data2

data3

Carry-In0

Carry-In1

Carry-Out0

Carry-Out1

PRN/ALDn

CLRn

LAB-Wide

Synchronous

Load

LAB-Wide

Synchronous

Clear

LE-Out

ENA

LAB-Wide

Clock Enable

Registered

Output

Combinatorial

Output

Sum

EP1M350 Datasheet(PDF) 21 Page - Altera Corporation

EP1M350 Datasheet(HTML) 21 Page - Altera Corporation

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