EP1M350 datasheet(79/86 Pages) ALTERA

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Altera Corporation

Mercury Programmable Logic Device Family Data Sheet

Notes to Tables 20 – 43.:

(1)

See the Operating Requirements for Altera Devices Data Sheet.

(2)

Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –0.5 V or overshoot to 4.1 V for input

currents less than 100 mA and periods shorter than 20 ns.

(3)

Maximum VCC rise time is 100 ms, and VCC must rise monotonically.

(4)

VCCIO maximum and minimum conditions for LVPECL, LVDS, RapidIO, and 3.3-V PCML are shown in

parentheses.

(5)

All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are

powered.

(6)

Typical values are for TA = 25° C, VCCINT = 1.8 V, and VCCIO = 1.8 V, 2.5 V, and 3.3 V.

(7)

These values are specified under the Mercury Device Recommended Operating Conditions shown in Table 3 on

page 3.

(8)

Input pins are grounded. In the test design, internal logic does not toggle. The test design does not use PLL or HSDI

circuitry. All ESBs are in power-down mode.

(9)

Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO.

(10) Drive strength is programmable according to values in Table 11 on page 53.

(11) For more information on termination, see AN 134: Using Programmable I/O Standards in Mercury Devices or

AN 159: Using HSDI in Source-Synchronous Mode in Mercury Devices.

(12) VREF specifies the center point of the switching range.

(13) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement

accuracy is within

±5%.

Timing Model

The high-performance multi-level FastTrack Interconnect routing

resources ensure predictable performance, accurate simulation, and

accurate timing analysis. The predictable performance of Mercury devices

offer an advantage over FPGAs, which use a segmented connection

scheme and therefore have unpredictable performance.

Figure 36 shows the timing model for bidirectional IOE pin timing. All

registers are within the IOE.

Figure 36. Synchronous Bidirectional Pin External Timing Model

PRN

CLRN

PRN

CLRN

PRN

CLRN

Dedicated

Clock

Bidirectional

Output Register

Input Register

OE Register

tINSUBIDIR

tOUTCOBIDIR

tXZBIDIR

tZXBIDIR

tINHBIDIR

EP1M350 Datasheet(PDF) 79 Page - Altera Corporation

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