HD6432138SW datasheet(312/1061 Pages) RENESAS

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Section 10 14-Bit PWM D/A

Rev. 4.00 Jun 06, 2006 page 258 of 1004

REJ09B0301-0400

Bits 15 to 3—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an

analog value is set in the upper 14 bits of the PWM D/A data register.

In each base cycle, the DACNT value is continually compared with these upper 14 bits to

determine the duty cycle of the output waveform, and to decide whether to output a fine-

adjustment pulse equal in width to the resolution. To enable this operation, the data register must

be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is

outside this range, the PWM output is held constant.

A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and

DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data

bits correspond to the two highest counter (DACNT) bits.

Bit 1—Carrier Frequency Select (CFS)

Bit 1

CFS

Description

Base cycle = resolution (T)

× 64

DADR range = H'0401 to H'FFFD

Base cycle = resolution (T)

× 256

DADR range = H'0103 to H'FFFF

(Initial value)

DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1.

DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are

located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS

bit can be accessed regardless of whether DADRB or DACNT is selected.

Bit 0

REGS

Description

DADRA and DADRB can be accessed

DACR and DACNT can be accessed

(Initial value)

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