HD6432138SW datasheet(310/1061 Pages) RENESAS

310 / 1061 page

Section 10 14-Bit PWM D/A

Rev. 4.00 Jun 06, 2006 page 256 of 1004

REJ09B0301-0400

10.2

10.2.1

PWM D/A Counter (DACNT)

R/W

Bit (CPU)

BIT (Counter)

Initial value

Read/Write

R/W

—

REGS

R/W

—

DACNTH

DACNTL

DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The

input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the

DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are

performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details.

DACNT functions as the time base for both PWM D/A channels. When a channel operates with

14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the

lower 12 (counter) bits and ignores the upper two (counter) bits.

DACNT is initialized to H'0003 by a reset, in the standby modes, watch mode, subactive mode,

subsleep mode, and module stop mode, and by the PWME bit.

Bit 1 of DACNTL (CPU) is not used, and is always read as 1.

DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are

located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS

bit can be accessed regardless of whether DADRB or DACNT is selected.

Bit 0

REGS

Description

DADRA and DADRB can be accessed

DACR and DACNT can be accessed

(Initial value)

HD6432138SW Datasheet(PDF) 310 Page - Renesas Technology Corp