HD6432138SW datasheet(311/1061 Pages) RENESAS

311 / 1061 page

Section 10 14-Bit PWM D/A

Rev. 4.00 Jun 06, 2006 page 257 of 1004

REJ09B0301-0400

10.2.2

D/A Data Registers A and B (DADRA and DADRB)

DA13

R/W

DA12

R/W

DA11

R/W

DA10

R/W

DA9

R/W

DA6

R/W

DA8

R/W

DA7

R/W

Bit (CPU)

Bit (Data)

DADRA

Initial value

Read/Write

DA5

R/W

DA4

R/W

DA3

R/W

DA2

R/W

DA1

R/W

—

DA0

R/W

—

CFS

R/W

DADRH

DADRL

DA13

R/W

DA12

R/W

DA11

R/W

DA10

R/W

DA9

R/W

DA6

R/W

DA8

R/W

DA7

R/W

DADRB

Initial value

Read/Write

DA5

R/W

DA4

R/W

DA3

R/W

DA2

R/W

DA1

R/W

REGS

R/W

DA0

R/W

CFS

R/W

There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA

corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read

and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,

data transfers between them and the CPU are performed using a temporary register (TEMP). See

section 10.3, Bus Master Interface, for details.

The least significant (CPU) bit of DADRA is not used and is always read as 1.

DADR is initialized to H'FFFF by a reset, and in the standby modes, watch mode, subactive mode,

subsleep mode, and module stop mode.

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