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HD6432138SW Datasheet(PDF) 308 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 308 Page - Renesas Technology Corp |
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308 / 1061 page  Section 10 14-Bit PWM D/A Rev. 4.00 Jun 06, 2006 page 254 of 1004 REJ09B0301-0400 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the PWM D/A module. Internal clock φ φ/2 PWX0 PWX1 DADRA DADRB DACNT DACR Legend: DACR: PWM D/A control register ( 6 bits) DADRA: PWM D/A data register A (15 bits) DADRB: PWM D/A data register B (15 bits) DACNT: PWM D/A counter (14 bits) Control logic Clock selection Clock Internal data bus Basic cycle compare-match A Fine-adjustment pulse addition A Basic cycle compare-match B Fine-adjustment pulse addition B Basic cycle overflow Comparator A Comparator B Bus interface Module data bus Figure 10.1 PWM D/A Block Diagram |
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