HD6432138SW datasheet(560/1061 Pages) RENESAS

560 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 506 of 1004

REJ09B0301-0400

The value of the BBSY bit cannot be modified directly by this module clear function, but since the

stop condition pin waveform is generated according to the state and release timing of the SCL and

SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and

flags may also have an effect.

To prevent problems caused by these factors, the following procedure should be used when

initializing the IIC state.

1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or

ICE bit clearing.

2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY

bit to 0, and wait for two transfer rate clock cycles.

3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or

ICE bit clearing.

4. Initialize (re-set) the IIC registers.

16.4

Usage Notes

• In master mode, if an instruction to generate a start condition is immediately followed by an

instruction to generate a stop condition, neither condition will be output correctly. To output

consecutive start and stop conditions, after issuing the instruction that generates the start

condition, read the relevant ports, check that SCL and SDA are both low, then issue the

instruction that generates the stop condition. Note that SCL may not yet have gone low when

BBSY is cleared to 0.

• Either of the following two conditions will start the next transfer. Pay attention to these

conditions when reading or writing to ICDR.

 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from

ICDRT to ICDRS)

 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from

ICDRS to ICDRR)

• Table 16.6 shows the timing of SCL and SDA output in synchronization with the internal

clock. Timings on the bus are determined by the rise and fall times of signals affected by the

bus load capacitance, series resistance, and parallel resistance.

HD6432138SW Datasheet(PDF) 560 Page - Renesas Technology Corp