HD6432138SW datasheet(564/1061 Pages) RENESAS

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Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 510 of 1004

REJ09B0301-0400

Time Indication (at Maximum Transfer Rate) [ns]

Item

cyc

Indication

Sr/tSf

Influence

(Max.)

2C Bus

Specifi-

cation

(Min.)

φφφφ =

5 MHz

φφφφ =

8 MHz

φφφφ =

10 MHz

φφφφ =

16 MHz

φφφφ =

20 MHz

SDAHO

cyc

Standard

mode

600

375

300

188

150

High-speed

mode

600

375

300

188

150

Notes: 1. Does not meet the I

2C bus interface specification. Remedial action such as the following

is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and

fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;

(d) select slave devices whose input timing permits this output timing.

The values in the above table will vary depending on the settings of the IICX bit and bits

CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the

maximum transfer rate; therefore, whether or not the I

2C bus interface specifications are

met must be determined in accordance with the actual setting conditions.

2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (t

SCLL –

cyc).

3. Calculated using the I

2C bus specification values (standard mode: 4700 ns min.; high-

speed mode: 1300 ns min.).

• Note on ICDR Read at End of Master Reception

To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1

and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is

high, and generates the stop condition. After this, receive data can be read by means of an

ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to

ICDR, and so it will not be possible to read the second byte of data.

If it is necessary to read the second byte of data, issue the stop condition in master receive

mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the

BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the

bus has been released, then read the ICDR register with TRS cleared to 0.

Note that if the receive data (ICDR data) is read in the interval between execution of the

instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the

actual generation of the stop condition, the clock may not be output correctly in subsequent

master transmission.

HD6432138SW Datasheet(PDF) 564 Page - Renesas Technology Corp

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