HD6432138SW datasheet(556/1061 Pages) RENESAS

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Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 502 of 1004

REJ09B0301-0400

Master receive mode

Read ICDR

Clear IRIC in ICCR

IRIC=1?

Clear IRIC in ICCR

Read IRIC in ICCR

IRIC = 1?

Last receive ?

Yes

Read ICDR

Read IRIC in ICCR

Clear IRIC in ICCR

IRIC = 1?

Last receive ?

Clear IRIC in ICCR

Read IRIC in ICCR

Clear IRIC in ICCR

Set ACKB = 1 in ICSR

Set TRS = 1 in ICCR

Clear IRIC in ICCR

Set WAIT = 0 in ICMR

Read ICDR

Write BBSY = 0

and SCP = 0 in ICCR

End

IRIC = 1?

Set TRS = 0 in ICCR

Set WAIT = 1 in ICMR

Set ACKB = 0 in ICSR

Read IRIC in ICCR

[1] Select receive mode

[2] Start receiving. The first read is a dummy

read. After reading ICDR, please clear

IRIC immediately.

[3] Wait for 1 byte to be received.

(8th clock falling edge)

[4] Clear IRIC to trigger the 9th clock.

(to end the wait insertion)

[5] Wait for 1 byte to be received.

(9th clock rising edge)

[6] Read the received data.

[7] Clear IRIC

[8] Wait for the next data to be received.

(8th clock falling edge)

[9] Clear IRIC

(to end the wait insertion)

[10] Set ACKB = 1 so as to return no

acknowledge, and set TRS = 1 so as not

to issue extra clock.

[12] Wait for 1 byte to be received.

[14] Stop condition issuance.

[13] Set WAIT = 0.

Read ICDR.

Clear IRIC.

(Note: After setting WAIT = 0, IRIC

should be cleared to 0)

[11] Clear IRIC

(to end the wait insertion)

Figure 16.15 Flowchart for Master Receive Mode (Example)

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