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HD6432138SW Datasheet(PDF) 553 Page - Renesas Technology Corp

Part # HD6432138SW
Description  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1061 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD6432138SW Datasheet(HTML) 553 Page - Renesas Technology Corp

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Section 16 I
2C Bus Interface [H8S/2138 Group Option]
Rev. 4.00 Jun 06, 2006 page 499 of 1004
REJ09B0301-0400
16.3.8
Operation Using the DTC
The I
2C bus format provides for selection of the slave device and transfer direction by means of
the slave address and the R/
W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 16.5 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 16.5
Examples of Operation Using the DTC
Item
Master Transmit
Mode
Master Receive
Mode
Slave Transmit
Mode
Slave Receive
Mode
Slave address +
R/
W bit
transmission/
reception
Transmission by
DTC (ICDR write)
Transmission by
CPU (ICDR write)
Reception by
CPU (ICDR read)
Reception by CPU
(ICDR read)
Dummy data
read
—
Processing by
CPU (ICDR read)
——
Actual data
transmission/
reception
Transmission by
DTC (ICDR write)
Reception by
DTC (ICDR read)
Transmission by
DTC (ICDR write)
Reception by DTC
(ICDR read)
Dummy data
(H'FF) write
——
Processing by
DTC (ICDR write)
—
Last frame
processing
Not necessary
Reception by
CPU (ICDR read)
Not necessary
Reception by CPU
(ICDR read)
Transfer request
processing after
last frame
processing
1st time: Clearing
by CPU
2nd time: End
condition issuance
by CPU
Not necessary
Automatic clearing
on detection of end
condition during
transmission of
dummy data (H'FF)
Not necessary
Setting of
number of DTC
transfer data
frames
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/
W bits)
Reception: Actual
data count
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Reception: Actual
data count



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