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HD6432138SW Datasheet(PDF) 554 Page - Renesas Technology Corp |
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HD6432138SW Datasheet(HTML) 554 Page - Renesas Technology Corp |
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554 / 1061 page  Section 16 I 2C Bus Interface [H8S/2138 Group Option] Rev. 4.00 Jun 06, 2006 page 500 of 1004 REJ09B0301-0400 16.3.9 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 16.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held. System clock period Sampling clock C DQ Latch C DQ Latch SCL or SDA input signal Match detector Internal SCL or SDA signal Sampling clock Figure 16.13 Block Diagram of Noise Canceler 16.3.10 Sample Flowcharts Figures 16.14 to 16.17 show sample flowcharts for using the I 2C bus interface in each mode. |
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