HD6432138SW datasheet(541/1061 Pages) RENESAS

541 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 487 of 1004

REJ09B0301-0400

Table 16.4

2C Bus Data Format Symbols

Legend

Start condition. The master device drives SDA from high to low while SCL is high

SLA

Slave address, by which the master device selects a slave device

Indicates the direction of data transfer: from the slave device to the master device

when R/

W is 1, or from the master device to the slave device when R/W is 0

Acknowledge. The receiving device (the slave in master transmit mode, or the master

in master receive mode) drives SDA low to acknowledge a transfer

DATA

Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-first or

LSB-first format is selected by bit MLS in ICMR

Stop condition. The master device drives SDA from low to high while SCL is high

16.3.2

Master Transmit Operation

In I

2C bus format master transmit mode, the master device outputs the transmit clock and transmit

data, and the slave device returns an acknowlede signal.

The transmission procedure and operations by which data is sequentially transmitted in

synchronization with ICDR write operations, are described below.

[1] Set the ICE bit in ICCR to l. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX

in STCR, according to the operation mode.

[2] Read the BBSY flag to confirm that the bus is free.

[3] Set the MST and TRS bits to 1 in ICCR to select master transmit mode.

[4] Write 1 to BBSY and 0 to SCP. This switches SDA from high to low when SCL is high, and

generates the start condition.

[5] When the start condition is generated, the IRIC and IRTR flags are set to 1. If the IEIC bit in

ICCR has been set to l, an interrupt request is sent to the CPU.

[6] Write data to ICDR (slave address + R/

With the I

2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first frame

data following the start condition indicates the 7-bit slave address and transmit/receive

direction.

Then clear the IRIC flag to indicate the end of transfer.

HD6432138SW Datasheet(PDF) 541 Page - Renesas Technology Corp