HD6432138SW datasheet(545/1061 Pages) RENESAS

545 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 491 of 1004

REJ09B0301-0400

then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be

generated.)

[14] Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and

generates the stop condition.

Bit7

Master receive mode

Master transmit mode

SCL

(master output)

SDA

(slave output)

SDA

(master output)

IRIC

IRTR

ICDR

User processing

[1] TRS cleared to 0

WAIT set to 1

ACKB cleared to 0

[2] ICDR read

(dummy read)

[2] IRIC clear

[4] IRIC clear

[6] ICDR read

(Data 1)

[7] IRIC clear

Bit6

Bit5

Bit4

Bit3

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

[3]

[5]

912

Data 1

Data 2

Data 1

Figure 16.8 (a) Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1)

Bit0

Data 2

SCL

(master output)

SDA

(slave output)

SDA

(master output)

IRIC

IRTR

ICDR

User processing

[9] IRIC clear

[6] ICDR read

(Data 2)

[7] IRIC clear

[9] IRIC clear

[6] ICDR read

(Data 3)

[7] IRIC clear

Bit7

[8]

[5]

Bit6

Bit5

Bit4

Bit7

Bit6

Bit3

Bit2

Bit1

Bit0

[8]

[5]

Data 3

Data 4

Data 3

Data 2

Data 1

Figure 16.8 (b) Example of Master Receive Mode Operation Timing

(MLS = ACKB = 0, WAIT = 1) (cont)

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