HD6432138SW datasheet(543/1061 Pages) RENESAS

543 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 489 of 1004

REJ09B0301-0400

SDA

(master output)

SDA

(slave output)

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 7

bit 6

IRIC

IRTR

ICDR

SCL

(master output)

Start condition

generation

Slave address

Data 1

[9] ICDR write

[9] IRIC clear

[6] ICDR write

[6] IRIC clear

address + R/W

[7]

[5]

Note: Data write

timing in ICDR

ICDR Writing

prohibited

[4] Write BBSY = 1

and SCP = 0

(start condition

issuance)

ICDR Writing

enable

Data 1

User processing

Figure 16.7 Example of Master Transmit Mode Operation Timing

(MLS = WAIT = 0)

16.3.3

Master Receive Operation

In master receive mode, the master device outputs the receive clock, receives data, and returns an

acknowledge signal. The slave device transrnits data.

The receive procedure and operations by which data is sequentially received in synchronization

with ICDR read operations, are described below.

[1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the

WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).

[2] When ICDR is read (dummy data read), reception is started and the receive clock is output,

and data is received, in synchronization with the internal clock. To indicate the wait, clear the

IRIC flag to 0.

Reading from ICDR and clearing of the IRIC f1ag must be executed continuously so that no

interrupt is inserted.

If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is

cleared, the end of transfer cannot be identified.

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