HD6432138SW datasheet(537/1061 Pages) RENESAS

537 / 1061 page

Section 16 I

2C Bus Interface [H8S/2138 Group Option]

Rev. 4.00 Jun 06, 2006 page 483 of 1004

REJ09B0301-0400

Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the

CPU when automatic format switching is executed for IIC channel 0.

Bit 4

Description

No interrupt is requested when automatic format switching is executed

(Initial value)

[Clearing condition]

When 0 is written in IF after reading IF = 1

An interrupt is requested when automatic format switching is executed

[Setting condition]

When a falling edge is detected on the SCL pin when SWE = 1

Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal

state of IIC0 and IIC1.

These bits can only be written to; if read they will always return a value of 1.

When a write operation is performed on these bits, a clear signal is generated for the internal latch

circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.

The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be

written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction

such as BCLR.

When clearing is required again, all the bits must be written to in accordance with the setting.

Bit 3

Bit 2

Bit 1

Bit 0

CLR3

CLR2

CLR1

CLR0

Description

——

Setting prohibited

IIC0 internal latch cleared

IIC1 internal latch cleared

IIC0 and IIC1 internal latches cleared

——

—

Invalid setting

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