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LIS331DL Datasheet(PDF) 33 Page - STMicroelectronics |
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LIS331DL Datasheet(HTML) 33 Page - STMicroelectronics |
33 / 42 page ![]() LIS331DL Register description 33/42 7.15 FF_WU_SRC_2 (35h) Free-fall and wake-up source register. Read only register. Reading at this address clears FF_WU_SRC_2 register and the FF_WU_2 interrupt and allows the refreshment of data in the FF_WU_SRC_2 register if the latched option was chosen. 7.16 FF_WU_THS_2 (36h) Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If DCRM=0 counter is reset when the interrupt is no more active else if DCRM=1 duration counter is decremented. Table 40. FF_WU_SRC_2 register -- IA ZH ZL YH YL XH XL Table 41. FF_WU_SRC_2 description IA Interrupt Active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) ZH Z High. Default value: 0 (0: no interrupt; 1: Z High event has occurred) ZL Z Low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) YH Y High. Default value: 0 (0: no interrupt; 1: Y High event has occurred) YL Y Low. Default value: 0 (0: no interrupt; 1: Y Low event has occurred) XH X High. Default value: 0 (0: no interrupt; 1: X High event has occurred) XL X Low. Default value: 0 (0: no interrupt; 1: X Low event has occurred) Table 42. FF_WU_THS_2 register DCRM THS6 THS5 THS4 THS3 THS2 THS1 THS0 Table 43. FF_WU_THS_2 description DCRM Resetting mode selection. Default value: 0 (0: counter reset; 1: counter decremented) THS6, THS0 Free-fall / wake-up Threshold. Default value: 000 0000 |
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Similar Description - LIS331DL_08 |
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