 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LIS331DL Datasheet(PDF) 19 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
LIS331DL Datasheet(HTML) 19 Page - STMicroelectronics |
|
|
19 / 42 page  LIS331DL Digital interfaces 19/42 5.1.1 I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the Master, the bus is considered busy. The next byte of data transmitted after the start condition contains the address of the slave in the first 7 bits and the eighth bit tells whether the Master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in the system compares the first seven bits after a start condition with its address. If they match, the device considers itself addressed by the Master. The Slave ADdress (SAD) associated to the LIS331DL is 001110xb. SDO/SA0 pad can be used to modify less significant bit of the device address. If SDO pad is connected to voltage supply LSb is ‘1’ (address 0011101b) else if SDO pad is connected to ground LSb value is ‘0’ (address 0011100b). This solution permits to connect and address two different accelerometers to the same I2C bus. Data transfer with acknowledge is mandatory. The transmitter must release the SDA line during the acknowledge pulse. The receiver must then pull the data line LOW so that it remains stable low during the HIGH period of the acknowledge clock pulse. A receiver which has been addressed is obliged to generate an acknowledge after each byte of data received. The I2C embedded inside the LIS331DL behaves like a slave device and the following protocol must be adhered to. After the start condition (ST) a slave address is sent, once a slave acknowledge (SAK) has been returned, a 8-bit sub-address will be transmitted: the 7 LSb represent the actual register address while the MSB enables address auto increment. If the MSb of the SUB field is 1, the SUB (register address) will be automatically incremented to allow multiple data read/write. The slave address is completed with a Read/Write bit. If the bit was ‘1’ (Read), a repeated START (SR) condition will have to be issued after the two sub-address bytes; if the bit is ‘0’ (Write) the Master will transmit to the slave with direction unchanged. Table 10 explains how the SAD+Read/Write bit pattern is composed, listing all the possible configurations. Table 10. SAD+Read/Write patterns Command SAD[6:1] SAD[0] = SDO/SA0 R/W SAD+R/W Read 001110 0 1 00111001 (39h) Write 001110 0 0 00111000 (38h) Read 001110 1 1 00111011 (3Bh) Write 001110 1 0 00111010 (3Ah) Table 11. Transfer when Master is writing one byte to slave Master ST SAD + W SUB DATA SP Slave SAK SAK SAK Table 12. Transfer when Master is writing multiple bytes to slave Master ST SAD + W SUB DATA DATA SP Slave SAK SAK SAK SAK |
Similar Part No. - LIS331DL_08 |
|
Similar Description - LIS331DL_08 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
