AD9788 datasheet(31/64 Pages) AD

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AD9785/AD9787/AD9788

Rev. 0 | Page 31 of 64

The interrupt control register comprises two bytes located at Address 0x09. Bits [11:10] and Bits [7:3] are read-only bits that indicate the

current status of a specific event that may cause an interrupt request (IRQ pin active low). These bits are controlled via the digital logic

and are read only via the serial port. Bits [1:0] are the IRQ mask (or enable) bits, which are writable by the user and can also be read back.

Table 19. Interrupt Control Register

Address

Bit

Name

Description

[15:13]

Reserved

Reserved for future use.

[12]

Clear lock indicator

Writing a 1 to this bit clears the sync lock lost status bit. This bit does not automatically

reset itself to 0 when the reset is complete.

[11]

Sync lock lost status

When high, this bit indicates that the device has lost synchronization. This bit is latched

and does not reset automatically after the device regains synchronization. To reset this

bit to 0, a 1 must be written to the clear lock indicator bit.

[10]

Sync lock status

When this bit is low, the device is not synchronized. When this bit is high, the device is

synchronized.

[9:8]

Reserved

Reserved for future use.

0: Default. No setup or hold time error has been detected via the input data port

setup/hold error checking logic.

[7]

Data timing error IRQ

1: A setup or hold time error has been detected via the input data port setup/hold error

checking logic.

0: Default. No setup or hold time error has been detected via the multichip

synchronization receive pulse setup/hold error checking logic.

[6]

Sync timing error IRQ

1: A setup or hold time error has been detected via the multichip synchronization

receive pulse setup/hold error checking logic.

0: Default. A hold error has been detected via the input data port setup/hold error

checking logic. This bit is valid only if the data timing error IRQ bit (Bit 7) is set.

[5]

Data timing error type

1: A setup error has been detected via the input data port setup/hold error checking

logic. This bit is valid only if the data timing error IRQ bit (Bit 7) bit is set.

0: Default. A hold error has been detected via the multichip synchronization receive

pulse setup/hold error checking logic. This bit is valid only if the sync timing error IRQ

bit (Bit 6) is set.

[4]

Sync timing error type

1: A setup error has been detected via the multichip synchronization receive pulse

setup/hold error checking logic. This bit is valid only if the sync timing error IRQ bit

(Bit 6) is set.

0: Default. The PLL clock multiplier is not locked to the input reference clock.

[3]

PLL lock indicator

1: The PLL clock multiplier is locked to the input reference clock.

[2]

Reserved

Reserved for future use.

0: Default. The data IRQ bit (and the IRQ pin) are not enabled (masked) for any errors

that may be detected via the input data port setup/hold error checking logic.

[1]

Data port IRQ enable

1: The data IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error is

detected via the input data port setup/hold error checking logic.

0: Default. The sync IRQ bit (and the IRQ pin) are not enabled (masked) for any errors

that may be detected via the multichip synchronization receive pulse setup/hold error

checking logic.

0x09

[0]

Sync port IRQ enable

1: The sync IRQ bit (and the IRQ pin) are enabled and go active if a setup or hold error

is detected via the multichip synchronization receive pulse setup/hold error checking

logic.

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