BS640HD8V datasheet(14/89 Pages) AMD

14 / 89 page

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A TA

SH EE T

active clock edge, and how the RDY signal will transi-

tion with valid data. The system would then write the

configuration register command sequence. See “Set

Configuration Register Command Sequence” section

on page 33 and “Command Definitions” section on

page 33 for further details.

Once the system has written the “Set Configuration

for synchronous reads only.

The initial word is output tIACC after the active edge of

the first CLK cycle. Subsequent words are output tBACC

after the active edge of each successive clock cycle,

which automatically increments the internal address

counter. Note that the device has a fixed internal

address boundary that occurs every 64 words, starting

at address 00003Fh. During the time the device is out-

putting data at this fixed internal address boundary

(address 00003Fh, 00007Fh, 0000BFh, etc.), a two

cycle latency occurs before data appears for the next

address (address 000040h, 000080h, 0000C0h, etc.).

The RDY output indicates this condition to the system

by pulsing low. For standard handshaking devices,

there is no two cycle latency between 3Fh and 40h (or

offset from these values by a multiple of 64) if the

latched address was 3Eh or 3Fh or offset from these

values by a multiple of 64). See Figure 46, “Latency

with Boundary Crossing,” on page 80.

For reduced wait-state handshaking devices, if the

address latched is 3Eh or 3Fh (or offset from these

values by a multiple of 64) two additional cycle latency

occurs prior to the initial access and the two cycle

latency between 3Fh and 40h (or offset from these

values by a multiple of 64) will not occur.

The device will continue to output sequential burst

data, wrapping around to address 000000h after it

reaches the highest addressable memory location,

until the system drives CE# high, RESET# low, or

AVD# low in conjunction with a new address. See

Table 1, “Device Bus Operations,” on page 11.

If the host system crosses the bank boundary while

reading in burst mode, and the device is not program-

ming or erasing, a two-cycle latency will occur as

described above in the subsequent bank. If the host

system crosses the bank boundary while the device is

programming or erasing, the device will provide read

status information. The clock will be ignored. After the

host has completed status reads, or the device has

completed the program or erase operation, the host

can restart a burst operation using a new address and

AVD# pulse.

If the clock frequency is less than 6 MHz during a burst

mode operation, additional latencies will occur. RDY

indicates the length of the latency by pulsing low.

8-, 16-, and 32-Word Linear Burst with Wrap Around

The remaining three modes are of the linear wrap

around design, in which a fixed number of words are

read from consecutive addresses. In each of these

modes, the burst addresses read are determined by

the group within which the starting address falls. The

groups are sized according to the number of words

read in a single burst sequence for a given mode (see

Table 2.)

Table 2.

Burst Address Groups

As an example: if the starting address in the 8-word

mode is 39h, the address range to be read would be

38 -3 Fh , and the b u rst se qu en ce w o uld b e

39-3A-3B-3C-3D-3E-3F-38h-etc. The burst sequence

begins with the starting address written to the device,

but wraps back to the first address in the selected

group. In a similar fashion, the 16-word and 32-word

Linear Wrap modes begin their burst sequence on the

starting address written to the device, and then wrap

back to the first address in the selected address group.

Note that in these three burst read modes the

address pointer does not cross the boundary that

occurs every 64 words; thus, no wait states are

inserted (except during the initial access).

The RDY pin indicates when data is valid on the bus.

The devices can wrap through a maximum of 128

words of data (8 words up to 16 times, 16 words up to

8 times, or 32 words up to 4 times) before requiring a

new synchronous access (latching of a new address).

Burst Suspend/Resume

The Burst Suspend/Resume feature allows the system

to temporarily suspend a synchronous burst operation

during the initial access (before data is available) or

after the device is outputting data. When the burst

operation is suspended, any previously latched internal

data and the current state are retained.

Burst Suspend requires CE# to be asserted, WE#

de-asserted, and the initial address latched by AVD# or

the CLK edge. Burst Suspend occurs when OE# is

de-asserted. See Figure 21, “Reduced Wait-state

Handshake Burst Suspend/Resume at an Even

Address,” on page 61, Figure 22, “Reduced Wait-state

Handshake Burst Suspend/Resume at an Odd

Address,” on page 61, Figure 23, “Reduced Wait-state

Handshake Burst Suspend/Resume at Address 3Eh

(or Offset from 3Eh),” on page 62, Figure 24, “Reduced

Wait-state Handshake Burst Suspend/Resume at

Mode

Group Size

Group Address Ranges

8-word

8 words

0-7h, 8-Fh, 10-17h,...

16-word

16 words

0-Fh, 10-1Fh, 20-2Fh,...

32-word

32 words

00-1Fh, 20-3Fh, 40-5Fh,...

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