BS640HD8V datasheet(7/89 Pages) AMD

7 / 89 page

May 10, 2006 27024B3

Am29BDS128H/Am29BDS640H

D A TA

SH EE T

PRODUCT SELECTOR GUIDE

Note: Speed Options ending in “8” indicate the “reduced wait-state handshaking” option, which speeds initial synchronous

accesses for even addresses. Speed Options ending in “9” indicate the “standard handshaking” option. See the AC

Characteristics section of this data sheet for full specifications.

BLOCK DIAGRAM

Note: Amax = A22 (128 Mb) or A21 (64 Mb)

Part Number

Am29BDS128H/Am29BDS640H

Burst Frequency

66 MHz

54 MHz

Speed Option

VCC, VIO = 1.65 – 1.95 V

E8, E9

D8, D9

Max Initial Synchronous Access Time, ns (TIACC)

Reduced Wait-state Handshaking; Even Address

Max Initial Synchronous Access Time, ns (TIACC)

Reduced Wait-state Handshaking; Odd Address; or Standard Handshaking

87.5

Max Burst Access Time, ns (TBACC)

13.5

Max Asynchronous Access Time, ns (TACC)

Max CE# Access Time, ns (TCE)

Max OE# Access Time, ns (TOE)

13.5

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC

Detector

State

Control

Command

VCC

VSS

VIO

WE#

RESET#

WP#

ACC

CE#

OE#

DQ15–DQ0

Data

Latch

Y-Gating

Cell Matrix

Amax–A0

RDY

Buffer

RDY

Burst

State

Control

Burst

Address

Counter

AVD#

CLK

BS640HD8V Datasheet(PDF) 7 Page - Advanced Micro Devices

BS640HD8V Datasheet(HTML) 7 Page - Advanced Micro Devices

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