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BS640HD8V Datasheet(PDF) 71 Page - Advanced Micro Devices

Part # BS640HD8V
Description  128 or 64 Megabit (8 M or 4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
PDF  89 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

BS640HD8V Datasheet(HTML) 71 Page - Advanced Micro Devices

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May 10, 2006 27024B3
Am29BDS128H/Am29BDS640H
69
D A TA
SH EE T
AC CHARACTERISTICS
Erase/Program Operations
Notes:
1.
Not 100% tested.
2.
Asynchronous mode allows both Asynchronous and Synchronous
program operation. Synchronous mode allows both Asynchronous
and Synchronous program operation.
3.
In asynchronous program operation timing, addresses are latched
on the falling edge of WE# or rising edge of AVD#. In synchronous
program operation timing, addresses are latched on the first of either
the falling edge of WE# or the active edge of CLK.
4.
See the “Erase and Programming Performance” section for more
information.
5.
Does not include the preprogramming time.
Parameter
Description
75 MHz
66 MHz
54 MHz
Unit
JEDEC
Standard
tAVAV
tWC
Write Cycle Time (Note 1)
Min
45
50
55
ns
tAVWL
tAS
Address Setup
Time (Notes 2,
3)
Synchronous
Min
45
ns
Asynchronous
0
tWLAX
tAH
Address Hold
Time (Notes 2,
3)
Synchronous
Min
5.5
6
7
ns
Asynchronous
15
20
20
tAVDP
AVD# Low Time
Min
10
12
ns
tDVWH
tDS
Data Setup Time
Min
20
45
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tGHWL
tGHWL
Read Recovery Time Before Write
Min
0
ns
tCAS
CE# Setup Time to AVD#
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
20
30
ns
tWHWL
tWPH
Write Pulse Width High
Min
15
20
20
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tVID
VACC Rise and Fall Time
Min
500
ns
tVIDS
VACC Setup Time (During Accelerated
Programming)
Min
1
µs
tVCS
VCC Setup Time
Min
50
µs
tELWL
tCS
CE# Setup Time to WE#
Min
0
ns
tAVSW
AVD# Setup Time to WE#
Min
4
5
ns
tAVHW
AVD# Hold Time to WE#
Min
4
5
ns
tACS
Address Setup Time to CLK (Notes 2, 3)
Min
4
5
ns
tACH
Address Hold Time to CLK (Notes 2, 3)
Min
5.5
6
7
ns
tAVHC
AVD# Hold Time to CLK
Min
4
5
ns
tCSW
Clock Setup Time to WE#
Min
5
ns
tSEA
Sector Erase Accept Timeout
Max
50
µs
tESL
Erase Suspend Latency
Max
35
µs
tASP
Toggle Time During Sector Protection
Typ
100
µs
tPSP
Toggle Time During Programming within a
Protected Sector
Typ
1
µs



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