BS640HD8V datasheet(22/89 Pages) AMD

22 / 89 page

Am29BDS128H/Am29BDS640H

27024B3 May 10, 2006

D A TA

SH EE T

grammed password. If they match, the PPB Lock bit is

cleared, and the PPBs can be altered. If they do not

match, the flash device does nothing. There is a

built-in 2 µs delay for each “password check.” This

delay is intended to thwart any efforts to run a program

that tries all possible combinations in order to crack

the password.

Password and Password Mode Locking Bit

In order to select the Password sector protection

scheme, the customer must first program the pass-

word. It is recommended that the password be

somehow correlated to the unique Electronic Serial

Number (ESN) of the particular flash device. Each ESN

is different for every flash device; therefore each pass-

word should be different for every flash device. While

programming in the password region, the customer

may perform Password Verify operations.

Once the desired password is programmed in, the

customer must then set the Password Mode Locking

Bit. This operation achieves two objectives:

1. It permanently sets the device to operate using the

Password Protection Mode. It is not possible to re-

verse this function.

2. It also disables all further commands to the pass-

word region. All program, and read operations are

ignored.

Both of these objectives are important, and if not care-

fully considered, may lead to unrecoverable errors.

The user must be sure that the Password Protection

method is desired when setting the Password Mode

Locking Bit. More importantly, the user must be sure

that the password is correct when the Password Mode

Locking Bit is set. Due to the fact that read operations

are disabled, there is no means to verify what the

password is afterwards. If the password is lost after

setting the Password Mode Locking Bit, there will be

no way to clear the PPB Lock bit.

The Password Mode Locking Bit, once set, prevents

reading the 64-bit password on the DQ bus and further

password programming. The Password Mode Locking

Bit is not erasable. Once Password Mode Locking Bit

is programmed, the Persistent Sector Protection Lock-

ing Bit is disabled from programming, guaranteeing

that no changes to the protection scheme are allowed.

64-bit Password

The 64-bit Password is located in its own memory

space and is accessible through the use of the Pass-

word Program and Verify commands (see “Password

Program Command” section on page 40 and “Pass-

word Verify Command” section on page 40). The

password function works in conjunction with the Pass-

word Mode Locking Bit, which when set, prevents the

Password Verify command from reading the contents

of the password on the pins of the device.

Persistent Protection Bit Lock

The Persistent Protection Bit (PPB) Lock is a volatile

bit that reflects the state of the Password Mode Lock-

ing Bit after power-up reset. If the Password Mode

Lock Bit is also set, after a hardware reset (RESET#

asserted) or a power-up reset the ONLY means for

clearing the PPB Lock Bit in Password Protection

Mode is to issue the Password Unlock command. Suc-

cessful execution of the Password Unlock command

clears the PPB Lock Bit, allowing for sector PPBs

modifications. Asserting RESET#, taking the device

through a power-on reset, or issuing the PPB Lock Bit

Set command sets the PPB Lock Bit to a “1”.

If the Password Mode Locking Bit is not set, including

Persistent Protection Mode, the PPB Lock Bit is

cleared after power-up or hardware reset. The PPB

Lock Bit can be set by issuing the PPB Lock Bit Set

command. Once set the only means for clearing the

PPB Lock Bit is by issuing a hardware or power-up re-

set. The Password Unlock command is ignored in Per-

sistent Protection Mode.

High Voltage Sector Protection

Sector protection and unprotection may also be imple-

mented using programming equipment. The procedure

requires high voltage (VID) to be placed on the

RESET# pin. Refer to Figure 2, “In-System Sector Pro-

tection/ Sector Unprotection Algorithms,” on page 22

for details on this procedure. Note that for sector unpro-

tect, all unprotected sectors must be first protected

prior to the first sector write cycle. Once the Password

Mode Locking bit or Persistent Protection Locking bit

are set, the high voltage sector protect/unprotect capa-

bility is disabled.

Standby Mode

When the system is not reading or writing to the device,

it can place the device in the standby mode. In this

mode, current consumption is greatly reduced, and the

outputs are placed in the high impedance state, inde-

pendent of the OE# input.

The device enters the CMOS standby mode when the

CE# and RESET# inputs are both held at VCC ± 0.2 V.

The device requires standard access time (tCE) for read

access, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active current until the opera-

tion is completed.

ICC3 in the “DC Characteristics” section on page 54

represents the standby current specification.

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