AT45DB041B-RU datasheet(15/35 Pages) ATMEL

15 / 35 page

3443C–DFLSH–5/05

AT45DB041B

11. AC Waveforms

Two different timing diagrams are shown below. Waveform 1 shows the SCK signal being low

when CS makes a high-to-low transition, and Waveform 2 shows the SCK signal being high

when CS makes a high-to-low transition. Both waveforms show valid timing diagrams. The setup

and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.

Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2 shows tim-

ing that is compatible with SPI Mode 3.

11.1

Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0

11.2

Waveform 2 – Inactive Clock Polarity High and SPI Mode 3

11.3

Reset Timing (Inactive Clock Polarity Low Shown)

Note:

The CS signal should be in the high state before the RESET signal is deasserted.

SCK

tCSS

VALID IN

tSU

tWH

tWL

tCSH

tCS

HIGH IMPEDANCE

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

SCK

tCSS

VALID IN

tSU

tWL

tWH

tCSH

tCS

HIGH Z

VALID OUT

tHO

tDIS

HIGH IMPEDANCE

SCK

RESET

HIGH IMPEDANCE

tRST

tREC

tCSS

AT45DB041B-RU Datasheet(PDF) 15 Page - ATMEL Corporation

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