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3443C–DFLSH–5/05

AT45DB041B

5.5

Pin Descriptions

5.5.1

Serial Input (SI)

The SI pin is an input-only pin and is used to shift data into the device. The SI pin is used for all

data input including opcodes and address sequences.

5.5.2

Serial Output (SO)

The SO pin is an output-only pin and is used to shift data out from the device.

5.5.3

Serial Clock (SCK)

The SCK pin is an input-only pin and is used to control the flow of data to and from the

DataFlash. Data is always clocked into the device on the rising edge of SCK and clocked out of

the device on the falling edge of SCK.

5.5.4

Chip Select (CS)

The DataFlash is selected when the CS pin is low. When the device is not selected, data will not

be accepted on the SI pin, and the SO pin will remain in a high-impedance state. A high-to-low

transition on the CS pin is required to start an operation, and a low-to-high transition on the CS

pin is required to end an operation.

5.5.5

Write Protect (WP)

If the WP pin is held low, the first 256 pages of the main memory cannot be reprogrammed. The

only way to reprogram the first 256 pages is to first drive the protect pin high and then use the

program commands previously mentioned. If this pin and feature are not utilized it is recom-

mended that the WP pin be driven high externally.

5.5.6

RESET

A low state on the reset pin (RESET) will terminate the operation in progress and reset the inter-

nal state machine to an idle state. The device will remain in the reset condition as long as a low

level is present on the RESET pin. Normal operation can resume once the RESET pin is brought

back to a high level.

The device incorporates an internal power-on reset circuit, so there are no restrictions on the

RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended

that the RESET pin be driven high externally.

5.5.7

READY/BUSY

This open drain output pin will be driven low when the device is busy in an internally self-timed

operation. This pin, which is normally in a high state (through a 1 k

Ω external pull-up resistor),

will be pulled low during programming operations, compare operations, and during page-to-

buffer transfers.

The busy status indicates that the Flash memory array and one of the buffers cannot be

accessed; read and write operations to the other buffer can still be performed.