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TUSB8043 Datasheet(PDF) 5 Page - Texas Instruments |
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TUSB8043 Datasheet(HTML) 5 Page - Texas Instruments |
5 / 59 page ![]() 5 TUSB8043 www.ti.com SLLSEW4 – JUNE 2017 Product Folder Links: TUSB8043 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions PIN I/O DESCRIPTION NAME NO. Clock and Reset Signals GRSTz 50 I PU Global power reset. This reset brings all of the TUSB8043 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional. XI 62 I Crystal input. This pin is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-M Ω feedback resistor is required between XI and XO. XO 61 O Crystal output. This pin is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-M Ω feedback resistor is required between XI and XO. USB Upstream Signals USB_SSTXP_UP 55 O USB SuperSpeed transmitter differential pair (positive) USB_SSTXM_UP 56 O USB SuperSpeed transmitter differential pair (negative) USB_SSRXP_UP 58 I USB SuperSpeed receiver differential pair (positive) USB_SSRXM_UP 59 I USB SuperSpeed receiver differential pair (negative) USB_DP_UP 53 I/O USB High-speed differential transceiver (positive) USB_DM_UP 54 I/O USB High-speed differential transceiver (negative) USB_R1 64 I Precision resistor reference. A 9.53-k Ω ±1% resistor should be connected between USB_R1 and GND. USB_VBUS 48 I USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-K Ω ±1% resistor, and to ground through a 10-k Ω ±1% resistor from the signal to ground. USB Downstream Signals USB_SSTXP_DN1 3 O USB SuperSpeed transmitter differential pair (positive) USB_SSTXM_DN1 4 O USB SuperSpeed transmitter differential pair (negative) USB_SSRXP_DN1 6 I USB SuperSpeed receiver differential pair (positive) USB_SSRXM_DN1 7 I USB SuperSpeed receiver differential pair (negative) USB_DP_DN1 1 I/O USB High-speed differential transceiver (positive) USB_DM_DN1 2 I/O USB High-speed differential transceiver (negative) PWRCTL1/BATEN1 36 I/O, PD USB Port 1 Power On Control for Downstream Power/Battery Charging Enable. The pin is used for control of the downstream power switch for Port 1. This pin be left unconnected if power management is not implemented. In addition, the value of the pin is sampled at the de-assertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging Support register: 0 = Battery charging not supported 1 = Battery charging supported OVERCUR1z 46 I, PU USB Port 1 Over-Current Detection. This pin is typically connected to the over current output of the downstream port power switch for Port 1. 0 = An over current event has occurred 1 = An over current event has not occurred When GANGED power management is enabled, this pin or one of the other OVERCURz pins must be connected to the over current output of the power switch or circuit which detects the over current conditions. For the case when another OVERCURz pin is used, this pin can be left unconnected. USB_SSTXP_DN2 11 O USB SuperSpeed transmitter differential pair (positive) USB_SSTXM_DN2 12 O USB SuperSpeed transmitter differential pair (negative) USB_SSRXP_DN2 14 I USB SuperSpeed receiver differential pair (positive) USB_SSRXM_DN2 15 I USB SuperSpeed receiver differential pair (negative) USB_DP_DN2 9 I/O USB High-speed differential transceiver (positive) USB_DM_DN2 10 I/O USB High-speed differential transceiver (negative) |
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