TPS73233DBVT datasheet(12/18 Pages) TI

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APPLICATION INFORMATION

INPUT AND OUTPUT CAPACITOR

OUTPUT NOISE

TPS732xx

GND

OUT

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

Optional output capacitor.

May improve load transient,

noise, or PSRR.

Optional bypass

capacitor to reduce

output noise.

+ 32mVRMS

) R2)

+ 32mVRMS

OUT

REF

(1)

TPS732xx

GND

OUT

OUT =

× 1.204

1 + R2)

Optional input capacitor.

May improve source

impedance, noise, or PSRR.

Optional output capacitor.

May improve load transient,

noise, or PSRR.

Optional capacitor

reduces output noise.

N(mVRMS)

+ 27

mVRMS

OUT(V)

(2)

N(mVRMS)

+ 8.5

mVRMS

OUT(V)

(3)

TPS73201, TPS73215, TPS73216

TPS73218, TPS73225, TPS73230

TPS73233, TPS73250

SBVS037F – AUGUST 2003 – REVISED SEPTEMBER 2004

The TPS732xx belongs to a family of new generation

LDO regulators that use an NMOS pass transistor to

REQUIREMENTS

achieve ultra-low-dropout performance, reverse cur-

rent blockage, and freedom from output capacitor

Although an input capacitor is not required for stab-

constraints. These features, combined with low noise

ility, it is good analog design practice to connect a

and an enable input, make the TPS732xx ideal for

0.1µF to 1µF low ESR capacitor across the input

portable applications. This regulator family offers a

supply near the regulator. This counteracts reactive

wide selection of fixed output voltage versions and an

input sources and improves transient response, noise

adjustable output version. All versions have thermal

rejection, and ripple rejection. A higher-value capaci-

and over-current protection, including foldback cur-

tor may be necessary if large, fast rise-time load

rent limit.

transients are anticipated or the device is located

several inches from the power source.

Figure 31 shows the basic circuit connections for the

fixed voltage models. Figure 32 gives the connections

The TPS732xx does not require an output capacitor

for the adjustable output version (TPS73201).

for stability and has maximum phase margin with no

capacitor. It is designed to be stable for all available

types and values of capacitors. In applications where

VIN - VOUT < 0.5V and multiple low ESR capacitors

are in parallel, ringing may occur when the product of

COUT and total ESR drops below 50nΩF. Total ESR

includes all parasitic resistances, including capacitor

ESR and board, socket, and solder joint resistance.

In most applications, the sum of capacitor ESR and

trace resistance will meet this requirement.

A precision band-gap reference is used to generate

the internal reference voltage, VREF. This reference is

Figure 31. Typical Application Circuit for

the dominant noise source within the TPS732xx and

Fixed-Voltage Versions

generates

approximately

32µVRMS

(10Hz

100kHz) at the reference output (NR). The regulator

control loop gains up the reference noise with the

same gain as the reference voltage, so that the noise

voltage of the regulator is approximately given by:

Since the value of VREF is 1.2V, this relationship

reduces to:

Figure 32. Typical Application Circuit for

for the case of no CNR.

Adjustable-Voltage Versions

An internal 27k

Ω resistor in series with the noise

reduction pin (NR) forms a low-pass filter for the

R1 and R2 can be calculated for any output voltage

voltage reference when an external noise reduction

using the formula shown in Figure 32. Sample re-

capacitor, CNR, is connected from NR to ground. For

sistor values for common output voltages are shown

CNR = 10nF, the total noise in the 10Hz to 100kHz

in Figure 2. For best accuracy, make the parallel

bandwidth is reduced by a factor of ~3.2, giving the

combination of R1 and R2 approximately 19kΩ.

approximate relationship:

for CNR = 10nF.

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