PIIX3 datasheet(5/122 Pages) INTEL

5 / 122 page

82371FB (PIIX) AND 82371SB (PIIX3)

2.5.1.9. DMA Memory Low Page Registers ....................................................................................... 65

2.5.1.10. DMA Clear Byte Pointer Register........................................................................................ 66

2.5.1.11. DMC—DMA Master Clear Register..................................................................................... 66

2.5.1.12. DCLM—DMA Clear Mask Register ..................................................................................... 66

2.5.2. TIMER/COUNTER REGISTER DESCRIPTION .......................................................................... 66

2.5.2.1. TCW—Timer Control Word Register..................................................................................... 66

2.5.2.2. Interval Timer Status Byte Format Register .......................................................................... 68

2.5.2.3. Counter Access Ports Register ............................................................................................. 69

2.5.3. INTERRUPT CONTROLLER REGISTERS ................................................................................. 69

2.5.3.1. ICW1—Initialization Command Word 1 Register................................................................... 70

2.5.3.2. ICW2—Initialization Command Word 2 Register................................................................... 70

2.5.3.3. ICW3—Initialization Command Word 3 Register................................................................... 71

2.5.3.4. ICW3—Initialization Command Word 3 Register................................................................... 71

2.5.3.5. ICW4—Initialization Command Word 4 Register................................................................... 71

2.5.3.6. OCW1—Operational Control Word 1 Register ...................................................................... 72

2.5.3.7. OCW2—Operational Control Word 2 Register ...................................................................... 72

2.5.3.8. OCW3—Operational Control Word 3 Register ...................................................................... 73

2.5.3.9. ELCR1—Edge/Level Triggered Register............................................................................... 74

2.5.3.10. ELCR2—Edge/Level Triggered Register............................................................................. 74

2.5.4. X-BUS, COPROCESSOR, and RESET REGISTERS ................................................................. 75

2.5.4.1. Reset X-Bus IRQ12 And IRQ1 Register................................................................................ 75

2.5.4.2. Coprocessor Error Register .................................................................................................. 75

2.5.4.3. RC—Reset Control Register ................................................................................................. 75

2.5.5. NMI REGISTERS ........................................................................................................................ 76

2.5.5.1. NMISC—NMI Status And Control Register ........................................................................... 76

2.5.5.2. NMI Enable and Real-Time Clock Address Register ............................................................. 77

2.6. System Power Management Registers .............................................................................................. 77

2.6.1. APMC—ADVANCED POWER MANAGEMENT CONTROL PORT ............................................. 77

2.6.2. APMS—ADVANCED POWER MANAGEMENT STATUS PORT ................................................ 78

2.7. PCI BUS Master IDE Registers .......................................................................................................... 78

2.7.1. BMICOM—BUS MASTER IDE COMMAND REGISTER ............................................................. 78

2.7.2. BMISTA—BUS MASTER IDE STATUS REGISTER ................................................................... 79

2.7.3. BMIDTP—BUS MASTER IDE DESCRIPTOR TABLE POINTER REGISTER ............................. 80

2.8. USB I/O Registers.............................................................................................................................. 80

2.8.1. USBCMD

USB Command Register........................................................................................... 80

2.8.2. USBSTS

USB Status Register.................................................................................................. 82

2.8.3. USBINTR

USB Interrupt Enable Register ................................................................................. 83

2.8.4. FRNUM

Frame Number Register.............................................................................................. 83

2.8.5. FLBASEADD

Frame List Base Address Register...................................................................... 84

2.8.6. Start Of Frame (SOF) Modify Register ........................................................................................ 84

2.8.7. PORTSC

Port Status and Control Register............................................................................... 85

3.0. FUNCTIONAL DESCRIPTION .............................................................................................................. 89

PIIX3 Datasheet(PDF) 5 Page - Intel Corporation

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