PIIX3 datasheet(42/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.17.

DLC—DETERMINISTIC LATENCY CONTROL REGISTER (Function 0) (PIIX3 Only)

Address Offset:

82h

Default Value:

00h

Attribute:

Read/Write

This register enables/disables the Delayed Transaction and Passive Release functions, respectively. When

enabled, these functions make the PIIX3 PCI revision 2.1 compliant. Note that neither delayed completion nor

passive release have any effect on bus master IDE and type F DMA transfers.

The 2.1 revision of the PCI specification requires much tighter controls on target and master latency. Targets

must respond with TRDY# or STOP# within 16 clocks of FRAME#, and masters must assert IRDY# within 8

PCI clocks for any data phase. PCI cycles to or from ISA typically take longer than this. The PIIX3 provides a

programmable

delayed completion mechanism described in the PCI specification to meet the required

target latencies.

ISA bridges also support GAT mode, which will now violate the spirit of the PCI specification. The PIIX3

provides a programmable

passive release mechanism to meet the required master latencies. When passive

release is enabled in the PIIX3, ISA masters may see long delays in accesses to any PCI memory, including

the main DRAM array. The ISA GAT mode is not supported with passive release enabled. ISA masters must

honor IOCHRDY.

Bit

Description

7:4

Reserved.

SERR# Generation Due To Delayed Transaction Timeout Enable. 1=Enable. 0=Disable.

USB Passive Release Enable (USBPR). 1=Enable

0=Disable.

Passive Release Enable. 1=Enable the Passive Release mechanism encoded on the

PHOLD# signal (default). 0=PHOLD# functions identically to the way it did in the PIIX

(82371FB).

Delayed Transaction Enable. 1=Enable the Delayed Transaction mechanism when the

PIIX3 is the target of a PCI transaction (default). 0=PIIX3 resonds as a target of a PCI

transaction identically to the way the PIIX (82371FB) responded.

PIIX3 Datasheet(PDF) 42 Page - Intel Corporation