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PIIX3 Datasheet(PDF) 26 Page - Intel Corporation |
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PIIX3 Datasheet(HTML) 26 Page - Intel Corporation |
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26 / 122 page  82371FB (PIIX) AND 82371SB (PIIX3) E 26 Table 4. PCI Configuration Registers—Function 2 (Universial Serial Bus Interface) (PIIX3 Only) Configuration Offset Mnemonic Register Register Access 00–01h VID Vendor Identification RO 02–03h DID Device Identification RO 04–05h PCICMD Command R/W 06–07h PCISTS Device Status R/WC 08h RID Revision Identification RO 09 −0Bh CLASSC Class Code RO 0Ch — Reserved — 0Dh LATTMR Latency Timer R/W 0Eh HEDT Header Type RO 0F–19h — Reserved — 20–23h BASEADD IO Space Base Address R/W 24–3Bh — Reserved — 3Ch IL Interrupt Line R/W 3Dh INTRP Interrupt Pin RO 3E–5Fh — Reserved. — 60h SBRNUM Serial Bus Release Number RO 61–69h — Reserved — 6A–6Bh MSTAT Miscellaneous Status R/W 6C–BFh — Reserved — C0–C1h LEGSUP Legacy Support R/WC C2–FFh — Reserved — |
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