PIIX3 datasheet(36/122 Pages) INTEL

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82371FB (PIIX) AND 82371SB (PIIX3)

2.2.10.

PIRQRC[A:D]—PIRQx ROUTE CONTROL REGISTERS (Function 0)

Address Offset :

60h (PIRQRCA#)—63h (PIRQRCD#)

Default Value:

80h

Attribute:

R/W

These registers control the routing of the PIRQ[A:D]# signals to the IRQ inputs of the interrupt controller.

Each PIRQx# can be independently routed to any one of 11 interrupts. All four PIRQx# lines can be routed to

the same IRQx input. Note that the IRQ that is selected through bits [3:0] must be set to level sensitive mode

in the corresponding ELCR Register. When a PIRQ signal is routed to an interrupt controller IRQ, the

PIIX/PIIX3 masks the corresponding IRQ signal.

Bit

Description

Interrupt Routing Enable. 0=Enable; 1=Disable

6:4

Reserved. Read as 0s.

3:0

Interrupt Routing. When bit 7=0, this field selects the routing of the PIRQx to one of the

interrupt controller interrupt inputs.

Bits[3:0]

IRQ Routing

Bits[3:0]

IRQ Routing

Bits[3:0]

IRQ Routing

0000

Reserved

0110

IRQ6

1011

IRQ11

0001

Reserved

0111

IRQ7

1100

IRQ12

0010

Reserved

1000

Reserved

1101

Reserved

0011

IRQ3

1001

IRQ9

1110

IRQ14

0100

IRQ4

1010

IRQ10

1111

IRQ15

0101

IRQ5

2.2.11.

TOM—TOP OF MEMORY REGISTER (Function 0)

Address Offset:

69h

Default Value:

02h

Attribute:

Read/Write

This register enables the forwarding of ISA or DMA memory cycles to the PCI Bus and sets the top of main

memory accessible by ISA or DMA devices. In addition, this register controls the forwarding of ISA or DMA

accesses to the lower BIOS region (E0000–EFFFFh) and the 512–640-Kbyte main memory region (80000–

9FFFFh). The Top Of Memory configuration register must be set by the BIOS.

Bit

Description

7:4

Top Of Memory. The top of memory can be assigned in 1-Mbyte increments from 1–16

Mbytes. ISA or DMA accesses within this region, and not in the memory hole region, are

forwarded to PCI.

Bits[7:4] Top of Memory

Bits[7:4]

Top of Memory

Bits[7:4]

Top of Memory

0000

1 Mbyte

0110

7 Mbyte

1011

12 Mbyte

0001

2 Mbyte

0111

8 Mbyte

1100

13 Mbyte

0010

3 Mbyte

1000

9 Mbyte

1101

14 Mbyte

0011

4 Mbyte

1001

10 Mbyte

1110

15 Mbyte

0100

5 Mbyte

1010

11 Mbyte

1111

16 Mbyte

0101

6 Mbyte

Note that the PIIX/PIIX3 only supports a main memory hole at the top of 16 Mbytes. Thus, If

a 1-Mbyte memory hole is created for the Host-to-PCI Bridge DRAM controller between 15

and 16 Mbytes, the PIIX/PIIX3 Top Of Memory should be set at 15 Mbytes.

PIIX3 Datasheet(PDF) 36 Page - Intel Corporation

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