PCINT8 datasheet(20/294 Pages) ATMEL

20 / 294 page

9219A–RFID–01/11

Atmel ATA5505 [Preliminary]

Timing diagrams for instruction fetch and execution are presented in Section 2.6 “Instruction

Execution Timing” on page 16.

Figure 3-1.

Program Memory Map

3.2

SRAM Data Memory

Figure 3-2 shows how the Atmel® AVR® SRAM Memory is organized.

The Atmel AVR is a complex microcontroller with more peripheral units than can be supported

within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the

Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be

used.

The data memory locations address both the Register File, the I/O memory, Extended I/O

memory, and the internal data SRAM. The first 32 locations address the Register File, the next

64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the

next locations address the internal data SRAM (see “ISRAM size” in Table 3-1 on page 19).

The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address

given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and

the internal data SRAM in the Atmel AVR are all accessible through all these addressing

modes. The Register File is described in “General Purpose Register File” on page 14.

0x0000

Flash end

Program Memory

PCINT8 Datasheet(PDF) 20 Page - ATMEL Corporation