C2.5X6.3MM-RAD datasheet(13/38 Pages) SILABS

13 / 38 page

Si3226/7

Si3208/9

Preliminary Rev. 0.33

Figure 2. PCM Highway Interface Timing Diagram

Table 12. Switching Characteristics—GCI Highway Serial Interface

(VDD = 3.13 to 5.25 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)

Parameter1

Symbol

Test

Conditions

Min

Typ

Max

Units

PCLK Period (2.048 MHz PCLK Mode)

—488

—

PCLK Period (4.096 MHz PCLK Mode)

—244

—

FSYNC Period2

tfs

—125

—

µs

PCLK Duty Cycle Tolerance

tdty

FSYNC Jitter Tolerance

tjitter

—

±120

Rise Time, PCLK

—

Fall Time, PCLK

—

Delay Time, PCLK Rise to DTX Active

td1

—

Delay Time, PCLK Rise to DTX Transition

td2

—

Delay Time, PCLK Rise to DTX Tristate3

td3

—

Setup Time, FSYNC Rise to PCLK Fall

tsu1

—

Hold Time, PCLK Fall to FSYNC Fall

th1

—

Setup Time, DRX Transition to PCLK Fall

tsu2

—

Hold Time, PCLK Falling to DRX Transition

th2

—

FSYNC Pulse Width

twfs

tp/2

—

Notes:

1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VO – 0.4 V and VIL =0.4 V.

Rise and fall times are referenced to the 20% and 80% levels of the waveform.

2. FSYNC source is assumed to be 8 kHz under all operating conditions.

3. Specification applies to PCLK fall to DTX tristate when that mode is selected.

PCLK

DRX

FSYNC

DTX

su 2

su 1

wf s

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