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SI8711CD-B-IM Datasheet(PDF) 15 Page - Silicon Laboratories |
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SI8711CD-B-IM Datasheet(HTML) 15 Page - Silicon Laboratories |
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15 / 36 page ![]() Si87xx Preliminary Rev. 0.5 15 New designs should consider the input circuit configurations of Figure 9, which are more efficient than those of Figures 7 and 8. As shown, S1 and S2 represent any suitable switch, such as a BJT or MOSFET, analog transmission gate, processor I/O, etc. Also, note that the Si87xx input can be driven from the I/O port of any MCU or FPGA capable of sourcing a minimum of 6 mA (see Figure 9B). Additionally, note that the Si87xx propagation delay and output drive do not significantly change for values of IF between IF(MIN) and IF(MAX). Figure 9. Si87xx Other Input Circuit Configurations 4.2. Output Circuit Design and Power Supply Connections The speed of the open collector circuit is dependent upon the supply, VCC, the pullup resistor, RL, and the load modeled by CL. Figure 10 illustrates three common circuit output configurations. For VDD = 5 V operation, RL>350 is recommended to ensure proper VOL levels. For VDD = 30 V operation, RL > 2.1 kis recommended to ensure proper VOL levels. If the enable pin is used (see Figure 10B) and two separate supplies power VDD and the VO pullup resistor, the enable pin should be referenced to the VDD pin because VO cannot exceed VDD by more than 0.5 V. Figure 10C illustrates a circuit using the internal 20 k resistor. Note that GND can be biased at, above, or below ground as long as the voltage on VDD with respect to GND is a maximum of 30 V. VDD decoupling capacitors should be placed as close to the package pins as possible. The optimum values for these capacitors depend on load current and the distance between the chip and its power source. It is recommended that 0.1 and 1 µF bypass capacitors be used to reduce high-frequency noise and maximize performance. Opto replacement applications should limit their supply voltages to 30 V or less. Figure 10. Si87xx Output Circuit Configurations Si87xx 1 2 3 4 +5V Control Input S1 N/C ANODE CATHODE N/C Si87xx A B R1 S2 4 N/C 3 CATHODE 2 MCU I/O Port pin ANODE R1 1 N/C Si87xx Si87xx B 5 GND 6 VO 7 VE 8 VDD 0.1, 1 µF EN VCC1 3-30 V RL CL VCC2 3-30 V C 5 GND 6 VO 7 8 RL CL 0.1, 1 µF VCC 3-30 V VL VDD Si87xx A 5 GND 6 VO 7 VE 8 VDD RL CL 0.1, 1 µF EN VCC 3-30 V |
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